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This brief presents a quarter-rate 1 finite impulse response and 1 infinite impulse response (IIR) direct decision feedback equalizer (DFE). The proposed non-time-overlapping data generation enables the elimination of all two-stacked clocked transistors in the 4:1 current-mode-logic multiplexer of conventional quarter-rate IIR DFEs. Therefore, the feedback delay is improved without static current in the multiplexer of this brief. Fabricated in a 65-nm CMOS, the DFE achieves a power efficiency of 0.43 pJ/b at a data rate of 10.8 Gb/s in 1-V supply. A BER < 10−12 for an eye width of 0.36 UI was verified over a 26-dB PCB channel loss. Core area is 0.00544 mm2.

This brief presents an input-data-jitter-tolerant injection-type clock and data recovery (CDR) circuit with a super-harmonic injection-locked ring oscillator (SH-ILRO). Unlike prior injection-type CDRs that utilize a power-hungry CML-type data injection path or for which the data rate is limited to the process-defined CMOS logic bandwidth, the proposed injection-type CDR achieves energy-efficient data edge injection. The proposed wide-bandwidth source follower-based edge detector extracts the input data edge energy efficiently. The proposed SH-ILRO enables quarter-rate injection-locking without high-speed injection selection logic. Fabricated in 65-nm CMOS, the prototype injection-type CDR consumes 19.08 mW at 12 Gb/s with 87-MHz jitter transfer bandwidth and more than 1.0 UIpp jitter tolerance at 20 MHz.

In this brief, a 0.9-V 12-Gb/s quarter-rate two finite impulse response tap direct decision feedback equalizer (DFE) is presented. For a high-speed incorporated operation of both DFE summing and slicing, a common-mode-controlled charge-based latch (CMCCBL) is proposed. In a CMCCBL-based DFE, the common mode of the first tap feedback signal is changed to adjust the first tap feedback weight. Therefore, CMCCBL does not need the conventional first tap weighting transistors which increase the DFE feedback delay. The DFE core compensates for the FR4 printed circuit board channel loss of −22 dB at 6 GHz and consumes 4.16 mW achieving 0.347 pJ/bit for PRBS7 input. The active area of DFE is 0.0036 mm2 in a 65-nm CMOS process.

This brief presents a 0.65-V power noise tolerant source-synchronous injection-locked receiver with 13.4 dB channel loss compensation. To meet the 1UI timing constraint for the decision feedback equalizer in low supply, SR latches are removed in the feedback path and return to zero recovered data is used for equalization. Additionally, a power noise sensitivity of low supply is relieved by current and pMOS body bias control techniques of an oscillator. The test core fabricated in 65-nm CMOS process achieves 11.2 Gb/s with 0.303 pJ/bit FOM compensating 13.4 dB channel loss at 5.6 GHz.

This brief presents a reference-less baud-rate digital clock and data recovery (CDR) with a data decision feedback (DDF) with a direct feedback method (DFM). The DDF with DFM has been used for the equalization of the channel loss for the serial link with a decision feedback equalizer. However, we apply DDF with DFM to the baud-rate CDR to reduce the number of data samplers, which is dropped to 2/3 compared to conventional baud-rate CDR. As a result, the power consumption and mismatch problem of the data samplers can be reduced. The test chip fabricated in 65-nm CMOS technology operates at a 10-Gb/s data rate with 13.84-mW power consumption.

Resistive RAM (ReRAM) is widely regarded as a promising platform for deep neural network (DNN) acceleration. However, the ReRAM device suffers from severe thermal problems that degrade the lifetime and inference accuracy of the ReRAM-based DNN accelerator. To address the issues, we propose a thermal-aware optimization framework for accelerating DNN on ReRAM (TOPAR). TOPAR includes 3-stage offline thermal optimization and online thermal-aware error compensation. Offline thermal optimization consists of thermal-aware weight decomposition, thermal-aware column reordering, and fine-grained weight adjustment to reduce the temperature of the ReRAM-based DNN accelerator. For online thermal-aware error compensation, we compensate conductance change according to the temperature variation. With TOPAR, the endurance degradation due to temperature rise improves up to 2.39×, and inference accuracy is preserved without harming the performance of the ReRAM-based DNN accelerator.

Convolutional neural network (CNN) is the most prominent algorithm for its wide usage and good performance. Despite the fact that the processing element (PE) plays an important role in CNN processing, there has been no study focusing on PE design optimized for state-of-the-art CNN algorithms. In this brief, we propose an optimal PE implementation including a data representation scheme, circuit block configurations, and control signals for energy-efficient CNN. To validate the excellence of this brief, we compared our proposed design with several previous methods, and fabricated a silicon chip. The software simulation results demonstrated that we can reduce 54% of data bit lengths with negligible accuracy loss. Our optimization on PE achieves to save computing power up to 47%, and an accelerator exploiting our method shows superior results in terms of power, area, and external DRAM access.

This paper presents a reference-less digital clock and data recovery (CDR) for liquid crystal display (LCD) intra-panel interfaces. The increments of the display resolution, the color depth, and frame rate demand high speed transmission capacity between timing controller and source driver IC (SDIC). As the data rate increases, the performances of the CDR in the SDIC especially for the tolerance of input jitter and ground noise become important to recover the data without an error. This work exploits the half-bit previous input data with feed forward method and early/late signal from CDR to be tolerant to the input jitter and power noise. Two prototypes are tested with half-rate clocking at 5 Gb/s data rate, and quarter-late clocking at 10 Gb/s data rate. Both 5 Gb/s and 10 Gb/s prototypes improve the tolerance of the input jitter and power noise. Fabricated in 65 nm CMOS technology, the test chips consume 17.44 mW and 20.7 mW, respectively.

A digital clock and data recovery (CDR) is presented, which employs a low supply sensitivity scheme for a digitally controlled oscillator (DCO). A coupling network comprising capacitors, resistors, and coupling buffers enhances the supply variation immunity of the DCO and mitigates the jitter performance degradation. A supply variation-dependent bias generator produces the corresponding bias voltage to alleviate the supply variation with minimal area and power penalty. The proposed scheme improves 29.3 ps of peak-to-peak jitter and 11.5 dB of spur level, at 6 and 5 MHz 50 mVpp sinusoidal supply noise tone, respectively. Fabricated in a 65-nm CMOS process, the proposed CDR operates at 5-Gb/s data rate with BER $ for PRBS 31 and consumes 15.4 mW. The CDR occupies an active die area of 0.075 mm2.

This paper presents a clock-path feedback equalization receiver with unfixed tap weighting property. In the proposed receiver, an equalization operation is achieved through a clock path so that a feedback loop delay is improved. Moreover, a feedback weight is changeable depending on the amount of inter-symbol interference (ISI) resulting in that a single tap compensates a high channel loss. Fabricated in a 65 nm CMOS, the receiver achieves a power efficiency of 0.376 mW/Gbps at a data rate of 12.5 Gb/s in 0.87 V supply. A BER

This brief presents a 2-GHz dividerless injection-locked phase-locked loop (PLL) (ILPLL) with a voltage-controlled oscillator (VCO) control voltage ripple-compensated phase detector (PD) (RICPD). The proposed lock detector (LD) can detect not only the frequency difference between VCO frequency and target frequency but also the coarse phase position. With the help of the LD, the RICPD has a simple architecture using AND gates, relieving mismatches in the PD and charge pump. Additionally, the RICPD improves the performance of phase noise by a ripple compensation technique and solves an UP/DN pulse mismatch problem of PLL with a simple structure. As a result, the proposed ILPLL improves jitter performance by 21% (471-fs integrated jitter from 1 kHz to 40 MHz). The test core fabricated in a 65-nm CMOS process consumes 6.2 mW.

This brief presents a power-efficient forwarded-clock receiver that is tolerant to high-frequency jitter by mixing filtered clock jitter to data. Due to mixing the filtered clock jitter, the proposed receiver does not include power-hungry delay lines but a phase interpolator, which enables saving significant power consumption. In a prototype receiver implemented in a 1-V 65-nm complementary metal–oxide–semiconductor process, it removes 2-GHz 0.7UI jitter modulated in data by an amount of 22%. It achieves 10 Gb/s with 0.71 pJ/bit in 10-cm FR4 channels and occupies 0.012 mm 2.

This brief presents an adaptive continuous-time linear equalizer (CTLE) and one-tap decision feedback equalizer (DFE) using the spectrum balancing (SB) method. The SB method is extended for not only CTLE but also DFE with the aid of gain characteristics of one-tap DFE. Thus, adaptation loops for each equalizer type are merged to a single loop. As a result, the complexity and power consumption of the adaptation circuits are reduced significantly. The test chip consumes 34.2 mW from 1.2 V supply with 65-nm CMOS process.

In this paper, a data-jitter mixing (DJM) forwarded-clock receiver is proposed that achieves high jitter correlation between data and a clock for high speed and small power consumption. The first-stage injection-locked oscillator (ILO) filters out high-frequency clock jitter that loses the correlation due to a latency mismatch between data and the clock. Then, a data-jitter mixer in the second stage of the proposed receiver further increases the jitter correlation reduced by nonoptimal jitter filtering in ILO. Moreover, the DJM reduces power supply noise induced jitter from a clock distribution network, while the conventional jitter filter cannot track the high-frequency jitter because of filtering it out. A prototype receiver implemented in 1-V 65-nm CMOS process achieves 9.6 Gb/s with 1.22-mW/Gb/s in spite of a 1.92-ns latency mismatch between data and a clock.

This paper presents a forwarded-clock receiver using a mixing cell integrated injection-locked oscillator (MIILO) and an I/Q generator based on injection-locked oscillator (IQGILO). By using MIILO, jitter tolerance is enhanced by about 1.8 times at high frequency compared to using a conventional injection-locked oscillator. In addition, the proposed receiver is robust against power supply induced jitter (PSIJ) caused by a clock distribution network because jitter tracking bandwidth of IQGILO is always lower than peak frequency of PSIJ regardless of latency mismatch between data and clock. The test chip achieves 9.6 Gb/s data rate with 0.96 mW/Gb/s and occupies only 0.0162 ${\rm mm}^{2}$ in a 1 V 65 nm CMOS.

As the data rate has been increased over 10 Gb/s with copper interconnect, the intersymbol interference (ISI) caused from the channel loss should be compensated. While a decision feedback equalizer (DFE), which is widely used in the receiver can compensate the ISI, its ability to enhance the signal-to-noise ratio (SNR) is limited especially for high frequency data patterns (alternating data patterns). Even a DFE with a large number of taps, which has powerful compensation capacity for ISI, can improve only limited amount of SNR. To improve SNR, this brief presents a 1/4th baud-rate continuous-time linear equalizer (CTLE) and a two-tap DFE. The 1/4th baud-rate CTLE recovers data to be adequate for the DFE, and remaining ISI is removed by the DFE. To boost the high frequency gain of the DFE, exclusive or merged adders are introduced, so the proposed equalizer is more tolerant against channel noise. It compensates 21.7-dB channel loss and operates with 11.5-Gb/s data rate as it consumes 25.35 mW from 1.3 V supply in a 110-nm CMOS technology.

Spatial thermal distribution of a chip is an essential information for dynamic thermal management. To get a rich thermal map, the sensor area is required to be reduced radically. However, squeezing the sensor size is about to face its physical limitation. In this background, we propose an area-efficient thermal sensing technique: hybrid temperature sensor network. The proposed sensor architecture fully exploits the spatial low-pass filtering effect of thermal systems, which implies that most of the thermal information resides in very low spatial frequency region. Our on-chip sensor network consists of a small number of accurate thermal sensors and a large number of tiny relative thermal sensors, responsible for low and high spatial frequency thermal information respectively. By combining these sensor readouts, a thermal map upsampler synthesizes a higher spatial resolution thermal map with a proposed guided upsampling algorithm.

A low power adaptive crosstalk cancellation for single-ended parallel interface is presented. A fast digital calibration which accurately detects the amount of crosstalk without a reference clock (reference-less) is proposed. To transfer calibration information from a receiver to a transmitter without additional channels, switched termination resistors (STR) are implemented. The reference-less adaptation and STR schemes achieve low power consumption and small area. A crosstalk compensator with simple structure is placed at transmitter-side, and it requires less design effort and low power. The proposed adaptive crosstalk cancellation scheme rapidly determines the optimum calibration point only during 4-cycle calibration time, and eliminates from 50% to 87.1% of the crosstalk-induced jitter (CIJ). It operates up to 5 Gbps consuming 1.6 mW/Gbps/CH in a 130 nm CMOS.

This paper presents a quarter-rate forwarded clock (FC) receiver based on an injection-locked oscillator (ILO) which exploits a phenomenon in which phases of the output clock are shifted by the duty-cycle of an injection clock. Also, this paper describes the principle of this phase shifting phenomenon. To utilize the phase shifting phenomenon, a simple duty-cycle adjuster (DCA) is proposed. By using the DCA, the proposed FC receiver achieves 760 MHz of wide jitter tracking bandwidth (JTB) and 60 MHz JTB variation in spite of clock deskew. The proposed receiver achieves a 12 Gb/s data rate with 0.92 mW/Gb/s in a 1 V 65 nm CMOS process.

A source synchronous architecture with constant and wide jitter-tracking bandwidth (JTB) is presented. The proposed receiver is based on an injection-locked oscillator (ILO), which provides jitter filtering and phase deskew simultaneously. While using only the ILO has intrinsic two dependence problems (JTB versus deskew and JTB versus a voltage-controlled oscillator tuning range required for 1 unit interval deskew), the proposed receiver makes them independent. Therefore, the proposed receiver can achieve the optimal JTB in a wide range supporting various applications by controlling deskew phase and JTB independently. A test chip was implemented to prove 11-Gb/s data recovery with constant 70-MHz to 1-GHz JTB in 0.13-μm CMOS.

This brief presents a line-on-glass-induced simultaneous switching noise (SSN)-tolerant transceiver for on-chip interconnects in a chip-on-glass-packaged source driver IC for TFT-LCDs. An SSN compensator generates noise-sensitive bias voltages to maintain the bandwidth of a receiver. With each 10 noise of and , the proposed circuit shows an eye width of 0.542 UI with a bit error rate (BER) of for 2-GB/s PRBS-7 while a conventional repeater shows an eye width of 0.132 UI with a BER of when and noises are injected.

A 5.4/2.7/1.62-Gb/s multi-rate receiver is designed for Display Port version 1.2. A dual-mode binary phase detector supports half-rate and quarter-rate phase detections to enable the multi-rate operation of the receiver without a wide-tuning VCO. In addition, a low voltage-drop active inductor with a voltage booster is implemented in the dual-mode binary phase detector to extend the bandwidth and reduce the power consumption. The voltage booster generates 1.904 V from 1.2-V supply with fast voltage generation time and small area consumption. A bandwidth controllable equalizer is proposed to optimize channel loss compensation even if the Nyquist frequency of input data changes. The BER for all input data rates is less than 10-12 for 27-1 PRBS and the measured jitter characteristics indicate that the proposed receiver exceeds the DisplayPort jitter tolerance specification. The recovered 1.35-GHz clock shows the peak-to-peak jitter of 29.9 ps and the rms jitter of 3.215 ps for 5.4-Gb/s input. The energy efficiency of the CDR circuit in the receiver is 19.3 pJ/bit at 5.4 Gb/s. The receiver occupies 0.672 mm2 including decoupling capacitors and the CDR core area is 0.44 mm2.

This paper presents a 5.4-Gb/s clock and data recovery circuit using a seamless loop transition scheme which has minimal phase noise degradation. The proposed scheme enables the CDR circuit to change the operation mode without output phase noise degradation or stability problems. A modified half-rate linear phase detector reduces the phase error between the data and clock. A tested chip is manufactured using 0.13-μm CMOS technology. The rms jitter of the proposed CDR circuit is 5.98 ps-rms, which is 2.61 ps lower than the CDR circuit with the conventional scheme. The measured power dissipation is 138 mW with output drivers and an embedded 2:1 MUX at 5.4-Gb/s data rate.

As modern high performance computing systems have various ICs associated together, one of the most appreciated architecture is direct path passing through the intermediate chips. Inter-chip and intra-chip communication are linked together in this architecture. Therefore to remove crosstalk induced noise and improve signal integrity, a novel CAC and corresponding CODEC which can be applied for both on-chip and off-chip channels is proposed. The proposed code does not require additional encoder and decoder at chip borders.

This brief presents an all-digital synchronous clock generator with an open-loop architecture, which achieves a fast lock and a wide range for mobile applications. The proposed architecture based on a clock-synchronized delay adopts a multipath delay line, which provides a high resolution and a low deterministic jitter with calibration circuits. A frequency range selector with a locking range moving technique achieves a wide-range operation. The proposed clock generator operates from 100 MHz to 1 GHz with a 14-ps peak-to-peak jitter performance at 1 GHz. The measured lock time is three to ten clock cycles depending on the operating frequency. The clock generator is implemented in a 0.18-μm CMOS process.

This brief presents a spread spectrum clock generator (SSCG) with a process variation compensator for DisplayPort main link. The process variation compensator reduces the error of spread ratio and guarantees reliable operation of an SSCG. The test chip has been implemented in 0.18-μm complementary metal-oxide-semiconductor process. The SSCG supports 10-phase 270- and 162-MHz clocks. The phase noise of an output clock at 270 MHz without spread spectrum clocking is -97.7 and -120.4 dBc/Hz at 1- and 10-MHz offset, respectively. The peak reduction is 8.75 dBm, and the spread ratio of 5000 ppm is achieved with a process variation compensator.

This brief presents a data-pattern-tolerant adaptive equalizer using the spectrum balancing method. In addition to a high-frequency boost control loop, this equalizer has a corner frequency control loop to guarantee its accurate adaptation for various data patterns and data rates. Measured results show that the jitter of the eye is reduced by a maximum of 37% when compared to the previous spectrum balancing equalizer. The chip is fabricated in a 0.18-?m CMOS process, and the equalizer core occupies 0.35 mm2 and consumes 85 mW.

A 6 Gb/s/pin transceiver for DRAM interfaces is implemented in a 0.13-mum CMOS process. Pseudo-differential signaling to overcome problems of conventional single-ended signaling is proposed. In a conventional single-ended signaling, the reference signal from a transmitter is generally used to reduce the common-mode noise which is induced by simultaneous switching noise (SSN). However, as supply voltage becomes low and data rate increases, the reference signal reduces the voltage and timing margin of receiver inputs. The proposed transceiver uses the pseudo-differential signaling without the reference signal and encoding schemes using the relation between neighboring data are proposed to remove the reference signal. In the receiver, transition-check circuit (TCC) is used to convert encoded data into original data before encoding. The proposed pseudo-differential signaling increases the eye-opening of 1:2 demuxed outputs of the receiver by 65 ps. The transceiver dissipates 242.5 mW and its active area is 1.0 mm times 0.3 mm.

A 5-Gb/s/pin transceiver for DDR memory interface is proposed with a crosstalk suppression scheme. The proposed transceiver implements a staggered memory bus topology and a glitch canceller to suppress crosstalk-induced distortions in a memory channel. The transceiver is implemented using 0.18 mum CMOS process and operates at 5 Gb/s. The results demonstrate widened eye diagram and lower bit error rate. The eye width and height of the proposed scheme increases 28.3% and 11.1% compared to the conventional memory transceiver, respectively. The peak-to-peak jitter of output data is 52.82 ps.

A DLL featuring jitter reduction techniques for a noisy environment is described. It controls a loop response mode by monitoring the magnitude of input jitter caused by supply noise. This technique varies the probability of phase error tracking. It reduces the output jitter of the DLL due to a low effective variance of input phase error and a narrow effective loop bandwidth. The DLL is implemented in a 0.13 mum CMOS process. Under noisy environments, the output clock of 1 GHz has 4.58 ps RMS and 29 ps peak-to-peak jitter.

In this paper, a 20 Gb/s 1:4 DEMUX without inductors is presented. A coupled latch with shared current source and buffer insertion scheme improves the signal bandwidth. A divide-by-2 circuit with a static frequency divider and a delay-locked loop achieves low power consumption and enhanced timing margin without the degradation of the divider sensitivity. A horizontal eye opening is 71.3%, and a vertical eye opening is 52%. The test chip fabricated in a 0.13 mum process consumes 210 mW from 1.2 V logic supply.

This paper presents a 2 GHz injection-locked PLL (ILPLL) with an injection-locked frequency divider (ILFD). Using a negative phase shift phenomenon of the ILFD, injection timing can be calibrated without a delay line. As a result, the proposed ILPLL achieves a simple background injection timing calibration for robustness of power supply variation. The test core has been fabricated in 65nm CMOS process consuming 3.74mW at 0.9V supply voltage.

This paper describes a novel integrated time register and arithmetic circuit (TRAC) for time-domain signal processing (TDSP). TRAC has four basic functions: time register, time adder, time subtractor, and time amplifier. One TRAC is able to accept multiple inputs and perform the combination of basic functions. Thus, complex arithmetic operations can be performed synchronously with a TRAC. In a synchronous time-to-digital converter (TDC), a high-gain residue amplifier with the suppressed offset-time component at the output can be implemented by exploiting the advantages of TRAC. The functions of TRAC are with post-layout data simulated in 110nm CMOS technology.

This paper describes a low-power read-only memory (ROM) using a single charge-sharing capacitor (SCSC) and hierarchical bit line (HBL). The SCSC-ROM reduces the power consumption in bit lines. It lowers the swing voltage of bit lines to a minimal voltage by using a charge-sharing technique with a single capacitor. It implements the capacitor with dummy bit lines to improve noise immunity and to make it easier to design. Furthermore, the HBL saves power by reducing the capacitance and leakage current in bit lines. The SCSC-ROM also reduces the power consumption in control unit and predecoder by using the hierarchical word line decoder. The simulation result shows that the SCSC-ROM with 4 K/spl times/32 bits consumes only 37% power of a conventional ROM. An SCSC-ROM chip is fabricated in a 0.25-/spl mu/m CMOS process. It consumes 8.2 mW at 240 MHz with 2.5 V.

This paper proposes a low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line. The pulsed NAND-NOR match-line not only significantly reduces the match-line power by activating only a few match-lines by using NAND cells for several bits but also achieves high speed by using NOR cells for most bits. The charge-recycling search-line driver reduces the search-line power by recycling the charge of search-lines without precharging. The CAM chip with 128/spl times/32 bit is fabricated in a 0.25-/spl mu/m CMOS process with 2.5 V. It dissipates 17.2 fJ/bit/search. It consumes 31% power of the dynamic NOR-type CAM.

This paper describes a wide-range delay-locked loop (DLL) for a synchronous clocking which supports dynamic frequency scaling and dynamic voltage scaling. The DLL has wide operating range by using multiple phases from its delay line. A phase detector (PD) which combines linear and binary characteristics achieves low jitter and fast locking speed. A pulse reshaper makes output pulses of the phase detector have variable pulsewidth and variable voltage level to mitigate the static phase error due to the inherent mismatch of the charge pump. The DLL operates in the range from 250 MHz to 2 GHz. At 1 GHz operating frequency, RMS jitter and peak-to-peak jitter are 1.57 ps and 10.7 ps, respectively.

This paper proposes a low power SRAM using hierarchical bit line and local sense amplifiers (HBLSA-SRAM). It reduces both capacitance and write swing voltage of bit lines by using the hierarchical bit line composed of a bit line and sub-bit lines with local sense amplifiers. The HBLSA-SRAM reduces the write power consumption in bit lines without noise margin degradation by applying a low swing signal to the high capacitive bit line and by applying a full swing signal to the low capacitive sub-bit line. The HBLSA-SRAM reduces the swing voltage of bit lines to V/sub DD//10 for both read and write. It saves 34% of the write power compared to the conventional SRAM. An SRAM chip with 8 K/spl times/32 bits is fabricated in a 0.25-/spl mu/m CMOS process. It consumes 26 mW read power and 28 mW write power at 200 MHz with 2.5 V.

A high-resolution synchronous mirror delay (SMD) is proposed in order to reduce the clock skew between the external clock and the internal clock of a chip. The proposed SMD reduces the clock skew in two steps. Coarse locking is achieved by the conventional SMD . Fine locking is achieved by the successive approximation register for the sake of fast locking . Measured results show that the maximum clock skew of the proposed SMD is 140 ps in the frequency range from 170 to 230 MHz and that the consumption power is 14.85 mW at 230 MHz in a 0.35-/spl mu/m 1-poly 4-metal CMOS technology. The total locking time is 10 clock cycles.

An 800-MHz low-power direct digital frequency synthesizer (DDFS) with an on-chip digital-to-analog (D/A) converter is presented. The DDFS consists of a phase accumulator, two phase-to-sine converters, and a D/A converter. The high-speed operation of the DDFS is enabled by applying parallelism to the phase-to-sine converter and by including a D/A converter in a single chip. The on-chip D/A converter saves delay and power consumption due to interchip interconnections. The DDFS considerably reduces power consumption by using several low-power techniques. The pipelined parallel accumulator consumes only 22% power of a conventional pipelined accumulator with the same throughput. The quad line approximation (QLA) and the quantization and error ROM (QE-ROM) minimize the ROM to generate a sine wave. The QLA saves 4 bits of the sine amplitude by approximating the sine function with four lines. The QE-ROM quantizes the ROM data by magnitude and address and then it stores the quantized values and the quantization errors separately. The ROM size for a 9-bit sine output is only 368 bits. A DDFS chip is fabricated in a 0.35-/spl mu/m CMOS process. It consumes only 174 mW at 800 MHz with 3.3 V. The chip core area is 1.47 mm/sup 2/. The spurious-free dynamic range (SFDR) is 55 dBc.

This paper describes CMOS time-domain temper- ature sensors. A principle of this type of sensors is CMOS invert- er's time-delay variation with temperature. The variation, how- ever, has nonlinearity which is a fundamental error source. Therefore, we propose a new temperature sensor that improves linearity using an injection-locked oscillator (ILO). Since the ILO has the opposite curvature of an inverter delay line in tempera- ture domain, nonlinear error induced by the CMOS inverters can be eliminated. Integral nonlinearity (INL) error is reduced from 3.6 LSB to 0.56 LSB (84% reduction), resulting in under 1-bit error by nonlinearity. The proposed design has -0.19℃~0.2℃ inaccuracy which is only quantization error over 0℃~100℃. The power consumption is 2.88mW including an 8-bit temperature- to-digital code conversion block at the sampling rate of 15.6M samples/s.

This brief presents a novel method to compensate a common electrode signal distortion caused by capacitive coupling between the data-lines and a common sheet electrode through a parasitic capacitor in TFT-LCD's. We designed a compensation circuit whose role is to give a negative feedback to the common electrode by detection of the amount of distortion and generation of the dependent voltage source to cancel off the distortion. By experiment, we found that the newly designed compensation circuit greatly reduced the distortion caused by crosstalk in large size line inversion TFT-LCD's.

Technology scaling and many-core design trends demand detailed information regarding the spatial temperature distribution, which is essential for dynamic thermal management [1,2]. The number of on-chip temperature sensors in high-performance processors is increasing, with state-of-the-art commercial processors embedding up to 44 on-chip sensors [3] and the number is likely to increase in the future (Fig. 14.7.1(a)). We observe two significant challenges in on-chip temperature sensing: 1) the increasing number of sensors, and 2) placing them in a regular manner (not solely on the potential hotspots). The number of sensors is mostly constrained by their area. Indeed, the sensor area is difficult to shrink since large delay lines or a BJT with a large ADC, and digital circuits are required to generate a proportional-to-absolute-temperature (PTAT) signal [2,5,6]. Many-core processor architectures give rise to the second challenge, namely, the hotspot locations within many-core processors are difficult to predict since we cannot determine the task allocation (and heat) profile at design time [2]. Consequently, an area-efficient dense thermal monitoring technique is desirable for next-generation processors.

For chip-to-chip parallel interfaces, maintaining low power consumption while achieving high aggregate bandwidth is the key trend. Forwarded-clock (FC) architecture is well suited to this trend because of the simple structure and inherent correlation of clock and data jitter [1]. Clock-recovery circuits consume a large portion of the I/O power. PLL/DLLs with a phase interpolator are widely used for the clock recovery circuits. However, they dissipate high power and jitter-tracking bandwidth (JTB) is low (PLL) or high (DLL), degrading the jitter correlation between data and clock. Recently, injection-locked oscillators (ILOs) have drawn much attention for the clock-recovery circuit of the FC interfaces due to their low power consumption [3-6]. By de-tuning the free-running frequency of an ILO, clock deskew can be performed and multiphase clocks can be generated without an additional multiphase generator. Also, ILOs can provide JTB of several hundred MHz, which is optimal for the FC interfaces in terms of the jitter correlation and BER [5].

This paper presents a data jitter mixing forwarded-clock receiver which is robust against power supply induced jitter (PSIJ) and overcomes 1.92ns latency mismatch between data and clock. The forwarded-clock architecture has a tradeoff between the number of clock channels and the achievable data rate due to the lack of the jitter correlation between data and clock. Moreover, PSIJ due to a long clock distribution network and an injection-locked oscillator reduces the jitter correlation further. The proposed receiver eases this tradeoff, and also increases the jitter correlation reduced by PSIJ. The test chip achieves 9.6Gb/s with 1.22mW/Gb/s and occupies only 0.017mm2 in 65nm CMOS.

This paper describes a 1-tap DFE with unfixed tap coefficient. According to the data patterns, the inter-symbol interference (ISI) is changed. The data patterns will be predicted using the DC level detector and the tap coefficient of the DFE will be adjusted to achieve high gain against high attenuation. The proposed 1-tap DFE with unfixed tap coefficient solves a high channel loss problem while it consumes low power. Designed in 65-nm CMOS technology, a 20 Gb/s receiver is composed of 1-tap half rate DFE with unfixed tap coefficient which compensates 20 dB attenuation, and it consumes 22.65 mW for 1-V supply.

The two-dimensional discrete cosine transform (2D DCT) has been widely recognized as a key processing unit for image data compression/decompression. In this paper, the implementation of a 200 MHz 13.3 mm/sup 2/ 8/spl times/8 2-D DCT macrocell capable of HDTV rates, based on a direct realization of the DCT, and using distributed arithmetic is presented. The macrocell, fabricated using 0.8 /spl mu/m base-rule CMOS technology and 0.5 /spl mu/m MOSFET's, performs the DCT processing with 1 sample-(pixel)-per-clock throughput. The fast speed and small area are achieved by a novel sense-amplifying pipeline flip-flop (SA-F/F) circuit technique in combination with nMOS differential logic. The SA-F/F, a class of delay flip-flops, can be used as a differential synchronous sense-amplifier, and can amplify dual-rail inputs with swings lower than 100 mV. A 1.6 ns 20 bit carry skip adder used in the DCT macrocell, which was designed by the same scheme, is also described. The adder is 50% faster and 30% smaller than a conventional CMOS carry look ahead adder, which reduces the macrocell size by 15% compared to a conventional CMOS implementation. >

This paper presents a forwarded clock receiver based on an injection-locked oscillator (ILO) with a simple clock multiplication unit to reduce the clock jitter and power consumption. The clock multiplication unit employs AC coupling and superposition technique to generate first-harmonic pulses. The first-harmonic injection reduces the rms and peak to peak jitter of the ILO output clock by about 0.65ps (29%) and 46.06ps (65%), respectively. The measured power efficiency of the receiver is 1.69mW/Gbps at 7.4Gb/s data rate in a 1.2V 0.13µm CMOS process.

This paper presents a 5.4 Gb/s clock and data recovery circuit using the seamless loop transition scheme which has no phase noise degradation. The controllable loop filter enables the CDR circuit to change the operation mode without the output phase noise degradation and the stability problem. The modified half-rate linear phase detector reduces the phase error between the data and clock. A tested chip is manufactured using 0.13 µm CMOS technology. The RMS jitter of the proposed CDR circuit is 5.98 ps-rms, which is 2.61 ps lower than the CDR circuit with the conventional scheme. The measured power dissipation is 138 mW with off-chip drivers at 5.4 Gb/s data rate.

This paper presents a fast-lock wide-range all-digital delay locked loops (ADDLL) for mobile applications. The proposed open-loop architecture based on time-to-digital converter (TDC) has a lock time of 3∼10 clock cycles. The multipath delay line is implemented to achieve high resolution in TDC. The frequency range selector is adopted for a wide-range operation. The ADDLL is implemented in a 0.18µm CMOS process and operates from 100MHz to 1GHz.

This paper presents a high resolution two-step gated-ring oscillator (TSGRO) time-to-digital converter (TDC) in an all digital phase-locked loop (ADPLL). TSGRO-TDC consists of a coarse step and a fine step gated-ring oscillator (GRO) TDC to achieve a high resolution. An edge aligner is used in the fine step GRO-TDC to enhance a first-order noise shaping property. A meta-stability free selection logic (MSFSL) is proposed in this paper which achieves low power and small area. In 0.13μm CMOS process, TSGRO-TDC has a 3ps raw resolution and first-order noise shaping.