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This paper presents a 100 MHz to 6 GHz broadband inductor-less single-to-differential balun gm-boosting low-noise amplifier (LNA) for multi-standard radio applications. Two mechanisms of noise cancellation techniques have been innovatively introduced in this work. To achieve the wideband input matching, high gain, and low noise figure simultaneously, a feed-forward thermal noise cancellation technique has been exploited in the design of the inverting amplifier for transconductance enhancement. Moreover, the balanced balun operation transforms the thermal noise of the common-gate transistor into a common-mode signal, and cancels it at the LNA’s differential outputs. The proposed design has been fabricated in a standard 0.18-um RF CMOS technology and occupies a die area of 0.04 mm2. Measurement results have shown that it has achieved a good performance over the whole operation frequency range of interest (100 MHz to 6 GHz) with a gain of 15.5 dB, IIP3 of 1.5 dBm, minimum NF of 3.0 dB and current dissipation of 8 mA at 1.8 V supply voltage.

This work presents a 24 ​GHz integrated Phase-Locked Loop in a 60 ​GHz sliding-IF transceiver for IEEE 802.15.3c standard with low phase noise. For low phase noise, a varactor and MOM cap combination method is applied in this 24 ​GHz PLL. The capacitor bank is optimized to decrease the noise folding from circuit noise to phase noise within this method. This analog PLL is fabricated in a 65 ​nm CMOS technology with a phase noise of −98.8 dBc/Hz@1 ​MHz, and the reference spur is −62.4 dBc. The power consumption of the PLL is 45.6 ​mW, including the output buffer.

An integrated fast hopping frequency synthesizer for ultra-wideband (UWB) cognitive radio (CR) is presented in this paper. Based on phase-locked loop (PLL) and single-side-band (SSB) mixing architecture, the frequency synthesizer covers 3.1~10.6 GHz band with a step of 528 MHz and a hopping time less than 9.8 ns. Distortion-cancelled I/Q calibration modules and multiplexers with poly-phase filters (PPF) are adopted to calibrate the I/Q imbalance of the SSB mixers and suppress the image spurs. To increase the bandwidth of the PLL and improve its in-band phase noise by reducing the loop division ratio, a quadrupler is introduced to multiply the crystal-oscillator frequency of 66 MHz to the reference frequency of 264 MHz. The proposed frequency synthesizer is designed in Global Foundry 0.13 µm 8HP SiGe BiCMOS process and its die area is 5.65 mm2. The simulation results have shown that the designed fast hopping frequency synthesizer exhibits hopping time < 8 ns, spurs < −40 dBc, phase noise < −103 dBc in band and < −116 dBc/Hz @ 1 MHz offset. Including the output buffers, the total power consume is 525 mW. The proposed fast hopping frequency synthesizer demonstrates a good performance and is suitable to implement in the UWB-based CR system.

A low voltage low power receiver supporting 780/868/915/2400 MHz ZigBee bands is presented in this paper. The receiver exploiting low-IF architecture consists of a RF-to-BB (baseband) current reuse front-end, a Gm-C based variable gain complex band-pass filter (CBPF) for image rejection and four stages of limiting amplifiers which saturate IF signal for demodulation. The proposed ZigBee receiver chip is implemented in TSMC 180 nm CMOS technology with metal-insulator-metal (MIM) capacitors. PCB measurement results show that the receiver has 45.9 dB conversion gain, 8.5 dB NF and −33.5 dBm out-of-band IIP3 at sub-GHz bands. When working in 2.4 GHz band, the gain is 38.4 dB, noise figure (NF) is 16.7 dB and the out-of-band IIP3 is −28.2 dBm. The S11 bandwidth (S11

A low power 0.1–1 GHz RF receiver front-end composed of noise-cancelling trans-conductor stage and I/Q switch stage was presented in this paper. The RF receiver front-end chip was fabricated in 0.18 µm RF CMOS. Measurement results show the receiver front-end has a conversion gain of 28.1 dB at high gain mode, and the single-sideband (SSB) noise figure is 6.2 dB. In the low gain mode, the conversion gain of the receiver front-end is 15.5 dB and the IP1dB is −12 dBm. In this design, low power consumption and low cost is achieved by current-reuse and inductor-less topology. The receiver front-end consumes only 5.2 mW from a 1.8 V DC supply and the chip size of the core circuit is 0.12 mm2.

In this paper, a newly analytical method is proposed for the design of programmable frequency dividers. The more accurate transfer function of the current mode logic (CML) stage is used to analyze the injection-locking behavior models of the dual-modulus prescaler, and the general analytical expressions of the locking range of the prescaler are derived. Based on the analytical expressions that can be calculated using device-level circuit parameters obtained through DC and AC simulations, the dual-modulus prescaler design can be optimized quickly and accurately, thereby extending the frequency-division range of the programmable frequency divider. The proposed analytical method is verified by the measured results of the 2–22 GHz programmable divider, fabricated in 0.13-μm SiGe BiCMOS technology. By using heterojunction bipolar transistors (HBTs) in the dual-modulus prescaler and metal–oxidesemiconductor field-effect transistors (MOSFETs) in the pulse and swallow counters, the proposed programmable divider achieves the lowest power consumption of 63.3 mW and the best FOMT compared with previously works.

An ultra-low-power (ULP) CMOS full-band (780/868/915/2400 MHz) ZigBee receiver front-end is presented. The front-end consists of a wideband common-gate LNA and an I/Q current-commutating mixer. Current reuse and active trans-conductance (gm ) boosting techniques are utilised in this design. Details on design and optimisation method for the proposed ULP receiver front-end are provided. Measurement results for 180 nm RF CMOS implementation show the front-end has a conversion gain of 25.2 dB at sub-GHz bands and 17.5 dB at 2.4 GHz band. The minimum noise figure at sub-GHz bands is 7.3 dB. The receiver front-end consumes only 0.826 mA from a 1.0 V DC supply and the size of the core circuit is 0.052 mm2.

This paper presents a highly-integrated transceiver with a differential structure for C-band (5–6[Formula: see text]GHz) radar application using a switchless and baluns-embedded configuration. To reduce the noise figure (NF) in receiver (Rx) mode and enhance the output power in transmitter (Tx) mode, the balun at RF port is embedded into the low-noise amplifier (LNA) and the power amplifier (PA), respectively. Besides, the RF switch is removed by designing the matching networks that both LNA and PA can share. The same topology is also adopted at the IF port. To achieve a high image rejection ratio (IRR), a Hartley architecture using polyphase filters (PPFs) is adopted. The proposed transceiver has been implemented in 1P6M 0.18-[Formula: see text]m CMOS process. The receiver achieves 6.9-dB NF, [Formula: see text]7.5-dBm IIP3 and 26.3-dB gain with three-step digital gain controllability. Also the measured IRR is better than 41[Formula: see text]dBc. The transmitter achieves 9.6-dBm output power and 19.2-dB gain. The chip consumes 106[Formula: see text]mA in the Rx mode and 141[Formula: see text]mA in the Tx mode from the 3.3-V power supply.

A wideband 2–3 GHz three-stage low noise amplifier (LNA) featuring current reuse, cascaded L-match input network, and multiple gated transistors method (MGTR) is designed in 0.18-μm CMOS technology. The current-reused topology is adopted to fulfill low power consumption, meanwhile, high gain and low noise are obtained. The cascaded L-match input network is used to enhance the input matching bandwidth. The MGTR is utilized to improve the linearity performance. Post-layout simulated results present a maximum power gain of 28.7 dB, a good input matching across 1.8–6.5 GHz and a high third-order input intercept point (IIP3) of-10.4 dBm. A noise figure (NF) of 3.1–3.3 dB is achieved within 2–3 GHz with a power dissipation of 6.2 mA from a 3 V power supply.

This paper presents a 24–48-GHz low power high gain low noise amplifier (LNA) in a 90-nm LP CMOS process. The asymmetrical T-coils, together with gate-inductive peaking, not only enhance the wideband gain, but also facilitate the layout design and reduce the chip area. The fabricated LNA circuit exhibits a broadband of 24–48-GHz and an average gain of 20 dB, while consuming a dc current of 17.6 mA from a 1.2 V supply. The minimum noise figure is only 3.1dB. This monolithic integrated circuit achieves excellent relative bandwidth of 67% compared with the previous published millimeter-wave (MMW) CMOS amplifiers.

This letter presents a wideband transformer balun with a center open stub. Since the interconnected line between two coupled-lines greatly deteriorates the performance of balun in millimeter-wave designs, the proposed center open stub provides a good solution to further optimize the balance of balun. The proposed transformer balun with center open stub has been fabricated in 90 nm CMOS technology, with a compact chip area of 0.012 mm 2 . The balun achieves an amplitude imbalance of less than 1 dB for a frequency band ranging from 1 to 48 GHz along with a phase imbalance of less than 5 degrees for the frequency band ranging from 2 to 47 GHz.

This paper presents the design of a low power and a highly linear folded down-conversion mixer, for wideband applications, implemented in a 65nm CMOS process. Post-layout simulation results are presented. The proposed multiple-gated transistor (MGTR) based mixer achieves a linearity enhancement of 12.68 dB when compared to a conventional folded single balanced mixer operating at an input radio frequency (RF) range of 10.25∼13.75 GHz (direct conversion), with a fixed local oscillator (LO) frequency of 12 GHz and a corresponding intermediate frequency (IF) ranging from dc∼1.75 GHz. The proposed mixer combines the advantages of both gm3 cancellation and low output impedance in order to maximize linearity without employing a tuned load, hence not limiting the performance of the mixer to narrowband applications.

This paper presents a fully integrated IF module which can receive or transmit signal with only one port. The switching time between reception and transmission is less than 3µs. In the state of reception, the IF module can convert differential signal to single-ended signal. Simulation results show 3.2dB power gain and 11.65dBm OP1dB while drawing 45mA from a 3.3V supply. In the state of transmission, the IF module can convert single-ended signal to differential signal. Simulation results show 0∼15dB programmable voltage gain and −3.5dBm IP1dB while drawing 16mA from a 3.3V supply. At working frequency of 1.3GHz∼1.4GHz, VSWRs can attain high performance in two states, both are less than 1.5∶ 1. The chip is designed in 0.18µm CMOS technology, the die area is 1.5*1.5 mm2. All the components of the linearization scheme are designed on-chip enabling maintenance of a single chip transceiver solution.

A 1.2V wide-band programmable divide-by-N frequency divider (FD) with consecutive 16-519 division ratios has been designed and fabricated using standard 90nm CMOS technology. The programmable FD consists of a high speed divide-by-8/9 dual-modulus prescaler, a pulse counter (P counter) and a swallow counter (S counter). Dynamic current-mode logic (DCML) DFF and signal locking technique have been used in this divider to achieve high speed operation. The proposed divider exhibits wide frequency range from 7GHz to 20.5GHz and dissipates 8.52mW power consumption at 1.2V voltage supply. Utilizing this FD, a charge-pump based PLL has been realized with 31.5GHz-34GHz frequency range. The phase noise of the PLL at 34.027GHz is −91.3dBc/Hz@1MHz offset. This PLL consumes 30.72mW power and occupies 1.32mm×1.01mm chip area.

This paper presents two new strain gauge bridge-to-pulse position modulation (PPM) converters. They have been developed in 2-/spl mu/m BiCMOS technology. The first one uses a chopper amplifier and a voltage-to-time converter associated in a feedback loop. This topology mainly exhibits an automatic offset cancellation capability, a ratiometric transfer function, and 10-b accuracy. The second one is a voltage-to-frequency converter using the switched-capacitor (SC) technique. It is an optimized version in terms of size minimization and noise rejection. Furthermore, a special RF transmitter has been designed in order to send the data from an intracorporal sensing and conditioning circuitry to an external computer dedicated to data analysis. Moreover, these converters are insensitive to offset drifts and are well suited for long term monitoring of orthopedic implants used for the treatment of bone fractures.

A fourth-order complex band-pass continuous-time filter with automatic tuning for a WSN transceiver is presented. The active transconductance-capacitor (Gm-C) filter was chosen for low power consumption and designed by series of two two-order filter units. The two-order filter is achieved with the source follower structure, which could get the image rejection as large as possible under the lowest power consumption. The center frequency and bandwidth deviation due to the process corner, aging and temperature deviation are adjusted by an automatic frequency tuning circuit. The core of the filter in a 0.18 μm RF CMOS technology consumes about 0.27 mA current from a 1.8 V power supply. The simulation results show that the bandwidth is about 2.2 MHz and the center frequency is about 2 MHz with automatic frequency tuning. The voltage gain of filter is about −0.8 dB, the ripple in the pass band is lower than 0.1 dB, and the image rejection ratio is larger than 30 dB at −2 MHz.

A fully integrated 5-GHz PLL frequency synthesizer for WSN applications has been designed and implemented in 0.18μm CMOS technology. With automatic current calibration technique (ACC), the VCO could maintain a good performance under a small current consumption of about 0.3mA. Phase switching technique is used in the frequency divider to reduce power consumption. Using a 1.8V supply voltage, the measured power consumption is 12mW and the phase noise is −111.13dBc/Hz at 1MHz offset.

This paper shows a low power low-noise mixer in RFCMOS 0.18μm technology that operates between 0.3–3.8GHz. The low power mixer has a Gilbert cell configuration which employs low-noise transconductors designed using the noise-cancelling technique. And the low-noise amplifier designs use the current-reused topology to reduce power consumption and employ a capacitive cross-coupled (CCC) gm-boosting to improve noise performance. This merged front-end achieves 11∼17dB power conversion gain, a flat SSB noise figure of 7.3∼11dB with IF 2MHz over the whole working range. It only consumes 1.69mA current from a 1.8V supply and its active area occupies only 0.04mm 2.

A 7-bit 26MS/s SAR (successive approximation register) ADC is presented in this paper for the application of ZigBee receiver. Compared to the conventional method, the set-and-down method reduces the average switching energy by around 80%. Dynamic comparator is chosen to diminish the signal-dependent offset caused by the non-fixed input common-mode voltage. A prototype ADC was implemented in a CMOS 0.18-μm technology. The ADC consumes 1.66 mW at 26MS/s under a 1.8-V supply. The post-simulation shows that SNDR and SFDR are 43.11dB and 57.49dB, when sampling 3.19921875 MHz sinusoid input signal at 26MHz sampling clock.

A 1.8 GHz LC VCO in 1.8-V supply is presented. The VCO achieves low power consumption by optimum selection of inductance in the L-C tank. To increase the tuning range, a three-bit switching capacitor array is used for digital switched tuning. Designed in 0.18μm RF CMOS technology, the proposed VCO achieves a phase noise of −126.2dBc/Hz at 1MHz offset and consumes 1.38mA core current at 1.8-V voltage supply.

A 2 GHz programmable frequency divider is presented in this paper for Chinese and American band WSN applications. The divide ratio can be programmed from 720 to 960. The divider basically consists of a 15/16 dual-modulus prescaler and a programmable pulse-swallow counter. Forward phase switching technique is used to reduce power consumption and avoid glitches. Designed in 0.18-μm CMOS process, the 15/16 prescaler and pulse-swallow occupies a chip area of approximately 60 μm ∗ 90 μm and 85 μm ∗ 85 μm. The post-layout simulation shows that the divider can operate under input frequency ranging from 1GHz to 3GHz and consume 3.24 mW from a single 1.8V supply.

In this paper, the design of a charge pump circuit suitable for lower power PLL-based frequency synthesizer is presented. The charge pump circuit was designed in 0.18μm CMOS process. The proposed charge pump circuit improves current matching in a wide output voltage range by applying a wide input ranged operational amplifier. The percentage error of current mismatch for the output range from 0.3V to 1.7V is less than ±0.005%. The power consumption of the proposed charge pump circuit is around 0.56mW at a supply voltage of 1.8V.

A 1V active-RC complex filter with on-chip automatic frequency tuning circuits for wireless sensor networks RF transceiver chip is designed using TSMC 0.18μm CMOS process. The filter is synthesized from a low-pass 3rd-order Chebyshev RLC ladder filter prototype. The filter is centered at 2MHz with a bandwidth of 3MHz. The simulated results show that the filter provides more than 30dB image rejection ratio while the ripple in the pass-band is less than 0.4dB. The filter consumes 3.9mA with 1V single supply voltage.

A fully integrated integer-N frequency synthesizer has been designed and implemented in 0.18μm RF CMOS technology for low intermediate frequency (IF) ZigBee transceiver application. It incorporates an automatic frequency calibration (AFC) loop to extend frequency tuning range. In-phase and quadrature (IQ) signals are generated by a divide-by-two frequency divider at the output of PLL. It consumes 11mA at 1.8V. The measured phase noise is −118dBc/Hz and −135dBc/Hz at the offset of 1MHz and 3MHz from 2.405GHz carrier respectively. The measured reference-spur at 2MHz offset from 2.405GHz carrier is −64dBc.

A 25.4-33.5 GHz wideband CMOS programmable multi-modulus divider with low power consumption is demonstrated. For a high operating frequency and low power consumption, a direct injection-locked frequency divider is used as the prescaler and followed directly by a dual-modulus divided-by-8/9 divider without any driving circuits. The dynamic-loading CML D flip-flips are utilised in the dual-modulus divider which further reduces the power consumption. Implemented in a 90 nm CMOS process, a frequency division from 542 to 654 in steps of 2 is achieved. Measurements show that the self-resonant frequency of the divider is 14.76 GHz, and the locking range is from 25.4 to 33.5 GHz for the total frequency division ratio at an input power of 0 dBm. The power consumption for the maximum division ratio and 0 dBm input power is 15.48 mW at a supply voltage of 1.2 V. The total chip size is 0.72 × 0.47 mm.

A 4.8GHz CMOS LC VCO with 37.5% tuning range in 0.5-V supply is presented. The VCO achieves low power consumption by optimum selection of inductance in the L-C tank. To increase the tuning range, a three-bit switching capacitor array is used for the digital switched tuning. A voltage-boosted technique is used to generate a high voltage for the switches in the digital tuning scheme. Designed in 0.13μm CMOS technology, the proposed VCO achieves a phase noise of −113.8dBc/Hz at 1MHz offset and consumes 2.4mA core current at 0.5 voltage supply.

A 5th-order Chebyshev active RC complex filter for wireless sensor networks with automatic frequency tuning is presented in this paper. This filter is synthesized from 5th-order low-pass LC prototype, and designed using leapfrog structure. An automatic frequency tuning is used to prevent the deviation of the RC constant of the filter. This filter is fabricated in TSMC 0.18μm CMOS process. The measurement results show that the passband gain of the filter is about 16dB and the ripple in the passband is about 1.5dB. It is centered at 2MHz with 2.45MHz of bandwidth after tuning. The image rejection ratio (IRR) is about 40dB and the adjacent channel rejuction (ACR) around 6MHz is about 55dB. The precision of the tuning system could be controlled to less than 3%. The filter consumes about 6.5mA totally with 1.8V power supply.

A 10-Gb/s transimpedance amplifier (TIA) for the parallel optical receiver module is realized in 0.18-μm CMOS technology. The proposed TIA employs a regulated cascode (RGC) input structure and adopts active inductor peaking and feedback techniques to enhance the bandwidth. Besides, a noise optimization is processed. The TIA provides a conversion gain of 50 dBΩ and 3-dB bandwith of 7 GHz. The measured sensitivity is about 35 μA at a bit error rate of 10−12 with a 231−1 pseudorandom test pattern for 10 Gb/s operation. Under a 1.8-V supply voltage, the differential TIA consumes 29.2 mW, counting an output buffer. The core chip area is 144×160 μm2 excluding the output buffer and testing pads.

In this paper, a new model for interleaved planar symmetric balun in CMOS radio frequency integrated circuits (RFICs) is developed. The model uses a “2-Π” sub-circuit to represent each inductor coil in the balun, and a novel substrate inductance is introduced to describe the substrate eddy-current effect. Verification with the measured data from a CMOS process demonstrates the model's accurate performance prediction up to self-resonant frequency (SRF).

This paper presents the design of a Class AB power amplifier (PA) for 2.4–2.4835GHz Wireless Sensor Network (WSN) system in 0.13µm CMOS technology. The PA adopts the single-stage differential structure and the output power of the PA can be controlled by switching the sizes of transistors. The proposed PA achieves a power added efficiency (PAE) of 25.34% while delivering an output power of 7.92dBm with an input power of −9.08dBm at 1dB compression point. The simulated maximum power gain is 18.09dB. With a DC voltage supply of 1.2V, the power consumption is 22.0mW. The layout size is 960×1120µm2.

This paper presented a RF model of an accumulation-mode MOS varactor for RF applications. Based on this model, simple and continuous equation has been used for describing the characteristics of the device in all operation regions. With a single topology composed of lumped elements, this model can be easily used in commercial circuit simulators. Based on S-parameter measurement, excellent agreement was obtained between measured data and model up to 40GHz.

A novel inductor model, which considers the magnetic and capacitive substrate coupling comprehensively, and a new fast approach for substrate network parameter extraction are presented in this paper. The introduction of substrate parasitic inductance (SPI) and the mutual inductance is based on the resonance characteristic of the measured substrate's Y-parameter and their physical meaning. A series of inductors were fabricated to build and verify the inductor model, using 0.13μm RF CMOS process. A good agreement between the measured data and model over a wide frequency range has been obtained.

A sensitive demodulator for Time-hopping Ultra Bandwidth (TH-UWB) radio frequency (RF) receiver is reported. The demodulator consists of a sensitive envelope detector, a voltage comparer, some signal amplifiers and a pulse shaper. The designs of the demodulator's circuit and layout are with 90-nm CMOS technology. The simulation results show that the demodulator can demodulate correctly the TH-UWB signals with a center frequency of 4 GHz and a bandwidth of more than 500 MHz, and an input voltage sensitivity of 3 mV. The whole system consumes 8 mW from a 1.2 V supply.

A g m -C complex filter with on-chip automatic tuning for wireless sensor networks (WSN) is designed using 0.18μm RF CMOS process. This filter is synthesized from a low-pass 5th-order Chebyshev RLC ladder filter prototype by means of capacitors and fully balanced transconductors with extended linear range. A conventional phase-locked loop (PLL) is used to realize the on-chip automatic tuning for both center frequency and bandwidth control. The filter bandwidth is 2.4MHz and is centered at 2MHz. The image band rejection is higher than 63dB while the ripple in the passband is less than 0.5dB. The complete filter including on-chip tuning circuit consumes less than 5mA with 1.8V single supply voltage.

A fully integrated voltage-controlled oscillator (VCO) for IEEE 802.11a WLAN transceivers is proposed and implemented in 0.18 μm CMOS technology with 1.8 V supply voltage. The VCO core adopts the topology of complementary cross-coupled differential inductance-capacitance (LC) tank. The VCO operates from 4.56 to 4.77 GHz with the varactor control voltage (Vtune) changing from 0.3 to 1.5 V and has a gain (Kv) of 175 MHz/V. A phase noise of -122.3 dBc/Hz at 1 MHz offset frequency is demonstrated for an oscillation frequency of 4.56 GHz. The average power consumption of this VCO is 30.24 mW.

A novel time-hopping ultra wideband (TH-UWB) signal generator is designed for TH-UWB communications. The generator consists of a 4-GHz oscillator and a switch with CMOS transmission gates. Through controlling the low frequency signals with time-hopping pulse position modulation (TH-PPM), the circuit outputs TH-UWB signals with wavelets. Implemented in 0.18-mum CMOS technology, the generator provides the amplitude of 65 mV at 50 Omega load from a 1.8-V supply, and can directly drive an antenna by a transmission line. Meanwhile, the output impedance is matched to 50 Omega. The simulation results indicate that the performance of the generator is good and meets the standard of IEEE 802.15.3a.

A RF CMOS front-end with high linearity for the GPS system is described. The LNA has a single-end input and a differential output, the mixer uses the intermodulation distortion (IMD) sinking technique. The front-end achieved -8.5 dBm input referred IP3 with 29.8 dB power gain, an input 1-dB compression point of -24 dBm, and a noise figure of 1.62 dB, consuming 8 mA from a 1.8 V supply.

In this paper, a fully integrated low noise amplifier (LNA) employing a cascode topology and an RC feedback network is proposed for an ultra-wideband (UWB) wireless system in a 0.18-mum RF CMOS technology. By using two single-stage cascode topologies, the function of both a single-end input and differential output is achieved. The wideband input impedance and noise matching is conducted by employing an RC feedback network, a degenerating inductor (Ls) and a gate one (Lg). The simulation results show that the average power gain (S21 or S31) is about 11 dB and the input return loss (S11) is less than -10 dB over the whole frequency range of 3 to 5 GHz. In addition, the noise figure (NF) is from 2.5 to 3.5 dB over 3-5 GHz while consuming 49 mW under a 1.8 V single supply voltage.

In this paper, a novel structure of linear-in-dB gain control is introduced. Based on this structure, a wideband variable gain amplifier has been designed and implemented in TSMC 0.18-mum RF CMOS process. On-chip measured results show a good linear-in-dB gain control characteristic with 12.8 dB dynamic gain range of -3.3~9.5 dB. It can operate in the frequency range of 43~2330 MHz and consumes 16.2 mW at 1.8 V supply. The noise figure is 6.2 dB at maximum gain and the input P1dB at minimum gain is -9 dBm.

A 900 MHz/1.9 GHz dual-band power amplifier driver (PA driver) in a 0.35 mum SiGe technology is presented. The PA driver has been designed for GSM/CDMA/PHS in- building applications. Simulation results show 31 dB voltage gain and 10.6 dBm OP 1 dB while drawing 36 mA from a 3.3 V supply. The size of the chip is 1.4times0.882 mm2.

This paper presents the design of a low power (LP) and a low noise figure (NF) quadrature demodulator with an on-chip frequency divider for quadrature local oscillator (LO) signal generation. The transconductance stage of the mixer is implemented by an AC-coupled self-bias current reuse topology. On-chip series inductors are employed at the gate terminals of the differential input transconductance stage to improve the voltage gain by enhancing the effective transconductance. The chip is implemented in 65-nm LP CMOS technology. The demodulator is designed for an input radio frequency (RF) band ranging from 10.25 to 13.75 GHz. A fixed LO frequency of 12 GHz down-converts the RF band to an intermediate frequency (IF) band ranging from DC to 1.75 GHz. From 10 MHz to 1.75 GHz the demodulator achieves a voltage conversion gain (VCG) ranging from 14.2 to 13.2 dB, and a minimum single-sideband NF (SSB-NF) of 9 dB. The measured third-order input intercept point (IIP 3 ) is -3.3 dBm for a two-tone test frequency spacing of 1 MHz. The mixer alone draws a current of only 2.5 mA, whereas the complete demodulator draws a current of 7.18 mA from a 1.2 V supply. The measurement results for a frequency divider, which was fabricated individually, prior to being integrated with the quadrature demodulator, in 65-nm LP CMOS technology, are also presented in this paper.

This paper presents a novel low noise amplifier (LNA) topology with image rejection (IR), called IRLNA. It achieves a high IR ratio using on-chip inductors with low quality factor. Two IRLNAs based on a standard 0.18-/spl mu/m CMOS technology are designed with L- and /spl pi/- resonant network, respectively. They have the same power consumption of 8 mW with one 1.8 V power supply. At the signal frequency of 5.25 GHz in the band of WLAN 802.11a, and with the image frequency at 3.25GHz, the simulation results show that the IR ratios achieve 71dB for L-resonant network and 92dB for /spl pi/-resonant network with on-chip inductors, and their noise figures are 1.4 dB and 1.7 dB, respectively.

In this paper, the design considerations and simulation results of a low-noise low-power radio frequency front end for 5-GHz WEAN receiver, which includes a low-noise amplifier and a downconversion mixer, are presented. Fabricated in 0.18-/spl mu/m CMOS technology, the front end achieves a noise figure of 1.4 dB, and a power gain of 28.4 dB while dissipating 11.2 mA from a 1.8-V supply.

This paper describes the design of a 1-GHz quadrature modulator for 802.11a WLAN systems with TSMC 0.18-/spl mu/m CMOS technology. By using an improved double-balanced mixer combined with a double-balanced mixer, a common-mode feedback circuit and an improved transconductance amplifier, the linearity of the modulator is improved. The experimental results show the modulator achieves -5 dBm for P/sub 1 dB/, -42 dB for LO-IF isolation, and a gain of 1.2 dB. The power consumption is 49 mW with a 1.8-V power supply.