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A new adiabatic circuit technique called adiabatic differential cascode voltage switch with complementary pass-transistor logic tree (ADCPL) is presented. ADCPL is a dual-rail logic with relatively low gate complexity. It operates from a two-phase nonoverlapping supply clock. Power reduction is achieved by recovering the energy in the recover phase of the supply clock. Energy dissipation comparison with other logic circuits is performed. Simulation shows that for a pipelined ADCPL carry lookahead adder, a power reduction of 50%-70% can be achieved over the static complimentary metal oxide semiconductor case within a practical operation frequency range. The results also show that the lower the operating frequency, the larger the energy savings for an ADCPL circuit. Index Terms--Adiabatic circuit, differential cascode voltage logic, low-power circuit, low-power digital system.

The significance of interfacial delamination as a crucial failure mechanism in electronic packaging has been documented in many papers. A number of failure criteria have been used to solve the problems with a pre-crack at the interface. However, in real electronic packages, the size and location of the cracks or/and delamination cannot be predicted. It is not easy to use the traditional fracture criteria to deal with more complicated 3D delamination problems. The epoxy molding compound (EMC)/copper leadframe interface was selected in this study. A series of button shear tests were conducted to evaluate the interfacial adhesion between the EMC and copper. In each test, the failure load acting on the EMC of the button shear sample was measured at different shear angles and a finite element model was used to evaluate the stresses at the EMC/copper interface. In this paper, an energy-based failure criterion is proposed using both the interfacial distortional and hydrostatic strain energy densities as two failure parameters. Stresses were extracted from the numerical simulation in order to calculate the interfacial distortional strain energy density, Ud, and the interfacial hydrostatic strain energy density, Uh, related, respectively, to the shear and tensile modes. Ud and Uh were averaged within a selected region of the finite element model where it exhibits high interfacial strain energy density values. [ABSTRACT FROM AUTHOR]

A planar double-gate SOI MOSFET (DG-SOI) with thin channel and thick source/drain (S/D) was successfully fabricated. Using both experimental data and simulation results, the S/D asymmetric effect induced by gate misalignment was studied. For a misaligned DG-SOI, there is gate nonoverlapped region on one side and extra gate overlapped region on the other side. The nonoverlapped region introduces extra series resistance and weakly controlled channel, while the extra overlapped region introduces additional overlap capacitance and gate leakage current. We compared two cases: bottom gate shift to source side (DG-S) and bottom gate shift to drain side (DG-D). At the same gate misalignment value, DG-S resulted in a larger drain-induced barrier lowering effect and smaller overlap capacitance at drain side than DG-D. Because of reduced drain-side capacitance, the speed of three-stage ring oscillator of DG-S, with 20% gate misalignment length (Lmis) is over gate length (Lg), or Lmis/Lg = 20%, was faster than that of two-gate aligned DG-SOI. [ABSTRACT FROM AUTHOR]

In this article, a generic VLSI architecture which is both programmable and scalable is proposed for block-matching motion estimation algorithms. Various motion estimation algorithms can be implemented using the proposed architecture by organizing the individual search positions (checking points) into checking vectors. A checking vector is processed in parallel by fully exploiting its data dependency. The optimal choice for the size of checking vector is discussed based on the design tradeoffs among processing speed, silicon area, and I/O bandwidth. Appropriate designs are recommended for various video applications. © 1998 John Wiley & Sons, Inc. Int J Imaging Syst Technol, 9, 257–273, 1998 [ABSTRACT FROM AUTHOR]

The electromigration (EM) properties of pure Cu and Cu/carbon nanotube (CNT) composites were studied using the Blech test structure. Pure Cu and Cu/CNT composite segments were subjected to a current density of 1.2 × 106 A/cm2. The average void growth rate of Cu/CNT composite sample was measured to be around four times lower than that of the pure copper sample. The average critical current-density-length threshold products of the pure Cu and Cu/CNT composites were estimated to be 1800 and 5400 A/cm, respectively. The slower EM rate of the CU/CNT composite stripes is attributed to the presence of CNT, which acts as trapping centers and causes a decrease in the diffusion of EM-induced migrating atoms. [ABSTRACT FROM AUTHOR]

Silicon oxynitride rectangular optical waveguides have been fabricated by plasma-enhanced chemical vapor deposition and dry etching. The propagation loss and polarization dependent loss in as-grown samples show a substantial reduction after the samples have been annealed. Birefringence measurements before and after annealing on waveguides of different widths suggest that the waveguide modal birefringence is strongly affected by both waveguide geometry and stress in the material. Hence, the modal birefringence can be minimized by designing the appropriate waveguide geometry to compensate for any stress effects. [ABSTRACT FROM AUTHOR]