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To enable accurate system-level electrostatic discharge (ESD) simulation, this article applies statistical learning to obtain I/O port models of the victim integrated circuits (ICs). A quasi-static I–V model derived using kernel regression can capture the circuit board dependency of the behavior observed at the I/O pin, regardless if there is snapback. The non-parametric kernel model can be reduced to a system-specific parametric model, which has smaller requirements for computing time and memory. In some cases, transient system-level ESD simulation may require the IC model to replicate the dynamic behavior of the nonlinear circuit. A recurrent neural network is demonstrated to be a suitable model in such cases. This article provides a detailed RNN training flow for IC pin modeling, and presents a Verilog-A implementation of the RNN for use with Simulation Program with Integrated Circuit Emphasis (SPICE)-type simulators. [ABSTRACT FROM AUTHOR]

On-chip supply noise induced by power-on ESD is studied with the aid of on-chip monitor circuits and circuit simulation. The monitor circuits’ outputs provide information about the magnitudes of the ESD-induced supply noise. The supply noise monitor circuits were implemented on a 130-nm CMOS test chip. Voltage monitor circuits record the maximum and minimum supply voltage excursions. Flip-flop monitor circuits respond to a rapid voltage change at the supply. Circuit simulation is used to validate hypotheses about how the noise spreads throughout the power delivery network. [ABSTRACT FROM AUTHOR]

Hundreds of static discharges were directed to a circuit board containing a custom test chip, and the resulting soft-failures were recorded. The large time-derivative of the ESD current is the primary cause of soft-failures in this system. Magnetic coupling between traces and bondwires produces glitches at IO pins; the magnitude of these glitches is increased by the bounce of the on-chip supply net relative to the on-board supply. Additionally, logic upsets due to substrate current collection are observed when the equipment-under-test is tethered, i.e., when it has a low impedance path to Earth-ground. [ABSTRACT FROM PUBLISHER]

Adaptive active bias conditioning (AABC) is proposed for high-speed inputs/outputs (I/O) to mitigate the tradeoff between bandwidth and electrostatic discharge (ESD) reliability. During a component-level ESD event, the I/O transistors’ gate voltages are adaptively set to the values that maximize ESD robustness based on the ESD polarity. The AABC technique has no deleterious effect on signal integrity or power consumption, because its circuitry is located off the high-speed signal path and activated only during ESD. The efficacy of the protection scheme is validated on a 130-nm complementary metal-oxide semiconductor test chip. Thirty percent improved ESD resiliency is found from the charged device model and very-fast transmission line pulsing tests with only 10% area overhead, relative to a transceiver with the same I/O protection and no AABC. In order to diagnose ESD-induced failures, a new failure analysis method, which utilizes power-on I – V curves, is introduced. Using this method, the failed device can be inferred without the use of any destructive, physical failure analysis techniques. [ABSTRACT FROM PUBLISHER]

An inherent CDM–electrostatic discharge (ESD) hazard exists in T-coil circuits due to magnetic coupling from the pad to the receiver input. An “inductance halving” technique is proposed to reduce magnetic coupling during ESD, thereby canceling voltage overshoot. Receiver circuits with continuous-time linear equalizers are placed on a 65-nm CMOS test chip to evaluate the performance of the proposed T-coil in comparison with the conventional T-coil with secondary ESD protection. From the eye diagram test using 25-Gb/s pseudorandom bit sequence data, the receiver with an inductance-halving T-coil shows 1.8× higher and 29% wider eye opening, as compared with the receiver with a T-coil protected by a secondary ESD device. In a very fast transmission line pulsing test, both schemes achieve around an 8-A failure current, which demonstrates that the proposed T-coil can effectively protect receiver circuits against CDM-like ESD stresses. [ABSTRACT FROM PUBLISHER]

This paper presents a methodology to construct an equivalent circuit model of a packaged integrated circuit mounted on a field-induced charged device model electrostatic discharge tester. Circuit simulation is used to obtain the full-component current and voltage distributions. This paper focuses on predicting overvoltage stress at power domain crossing circuits. [ABSTRACT FROM PUBLISHER]

The interdie signal interfaces in a three-dimensional (3-D) integrated circuit are vulnerable to overvoltage stress induced by charged device model (CDM) ESD, although they do not necessarily lie on any of the main ESD current paths. Circuit simulation shows that the magnitude of the stress is highly sensitive to the design of the ground distribution network on both the die and package levels. The placement of TSVs also impacts the stress generated at the interdie interfaces. If excessive, the voltage stress can be mitigated by placing a small ESD clamp at the interdie signal interface. A power supply domain may span multiple dies in a 3-D stack; this work investigates whether it is possible to remove the clamps from some of the dies in the stack to save silicon area without severely impacting the CDM reliability of the interdie interface circuits. [ABSTRACT FROM PUBLISHER]

An active rail clamp circuit provides protection against component-level ESD; this work explores the challenges associated with designing a rail clamp to additionally provide protection when the IC is powered on. The fast transient response required to protect against ESD makes it difficult to design a stable circuit and introduces tradeoffs between supply integrity and the clamping characteristic. This work presents an analysis of how these performance metrics are affected by device sizes. Interactions between a rail clamp circuit, which may be an active or passive clamp, and the parasitic elements of the package and board are examined; it is shown that these interactions may briefly power down the supply. [ABSTRACT FROM PUBLISHER]

This work presents a new type of model, i.e., piecewise-linear model with transient relaxation (PWL-TR), to describe the nonlinear transient characteristics of electrostatic discharge (ESD) protection devices and circuits. The PWL-TR model represents the device as a finite-state machine; hence, no proprietary information is disclosed. The PWL-TR model offers accuracy comparable to a compact model but enables more computationally efficient simulation. [ABSTRACT FROM PUBLISHER]

Two 3.65-mW, ESD-protected, BiCMOS ultra-wideband low-noise amplifiers (LNAs) for operation up to 10 GHz are presented. These common-base LNAs achieve significant savings in die area over more widely used cascoded common-emitter LNAs because they do not use an LC input matching network. A design with a shunt peaked load achieves a high S21 (17-19 dB) and low noise figure (NF) (4-5 dB) across the band. A resistively loaded design exhibits a lower S21 (15-16 dB) and higher NF (4.5-6 dB), but also utilizes 20% less silicon area. Both LNAs achieve a 1.5 kV ESD protection level and an acceptable S11 (<-10 dB) across the band. Current source noise reduction is critical in common base topologies. Therefore, detailed noise analyses of MOS- and HBT-based current sources are provided. [ABSTRACT FROM AUTHOR]

This work presents a model for multi-finger MOSFETs operating under ESD conditions. It is a distributed model that can reproduce the effect of layout geometry on trigger voltage, on-state resistance, and non-uniform turn-on of device fingers. A three-terminal transmission line pulsing technique enables model parameter extraction. Analysis of measurement data and TCAD simulation reveals that self-heating is not uniform across the device, and this affects the relation between on-state resistance and the number of fingers. With self-heating incorporated, the model correctly reproduces the device I–V curve up to high current levels. [ABSTRACT FROM AUTHOR]