Search

Conventional charge-based memory usage in low-power applications is facing major challenges. Some of these challenges are leakage current for static random access memory (SRAM) and dynamic random access memory (DRAM), additional refresh operation for DRAM, and high programming voltage for Flash. In this paper, two emerging resistive random access memory (ReRAM) technologies are investigated, memristor and spin-transfer torque (STT)-RAM, as potential universal memory candidates to replace traditional ones. Both of these nonvolatile memories support zero leakage and low-voltage operation during read access, which makes them ideal for devices with long sleep time. To date, high write energy for both memristor and STT-RAM is one of the major inhibitors for adopting the technologies. The primary contribution of this paper is centered on addressing the high write energy issue by trading off retention time with noise margin. In doing so, the memristor and STT-RAM power has been compared with the traditional six-transistor-SRAM-based memory power and potential application in wireless sensor nodes is explored. This paper uses 45-nm foundry process technology data for SRAM and physics-based mathematical models derived from real devices for memristor and STT-RAM. The simulations are conducted using MATLAB and the results show a potential power savings of 87% and 77% when using memristor and STT-RAM, respectively, at 1% duty cycle.

These days, microservice architecture is widely used in the design and development of many real-time, critical, and large-scale online services. These services are typically deployed using Docker containers on cloud platforms. Container technology supports the deployment of these services with high portability, scalability, and performance, when compared to deploying them using virtual machines (i.e. VM-based services). It is widely known fact that container-based services give better performance than VM-based services. However, we show in this paper that services deployed using Amazon AWS ECS (EC2 Container Service) surprisingly perform significantly worse when compared with services deployed using Amazon EC2 VMs. We study and quantify the performance difference in terms of throughput, response time and CPU utilization considering different deployment scenarios.

This paper presents the design, analysis, simulation and implementation of the architecture of a new non-uniform type digital phaselocked loop (DPLL). The proposed loop uses a composite phase detector (CPD), which consists of a sample-and-hold unit and an arctan block. The CPD improves the system linearity and results in a wider lock range. In addition, the loop has an adaptive controller block, which can be used to minimize the overall system sensitivity to variations in the power of the input signal. Furthermore, the controller has a tuning mechanism that gives the designer the flexibility to customize the loop parameters to suit a particular application. These performance parameters include lock range, acquisition time, phase noise or jitter, and signal to noise ratio enhancement. The simulation results show that the proposed loop provides flexibility to optimize the major conflicting system parameters. A prototype of the proposed system was implemented using an FPGA and the practical results concur with those obtained by simulation using MATLAB/Simulink.

The mathematical analysis of the convergence behaviour of the first-order single channel digital tanlock loop (SC-DTL) is presented. This article also describes a novel technique that allows controlling the convergence speed of the loop, i.e. the time taken by the phase-error to reach its steady-state value, by using a specialised controller unit. The controller is used to adjust the convergence speed so as to selectively optimise a given performance parameter of the loop. For instance, the controller may be used to speed up the convergence in order to increase the lock range and improve the acquisition speed. However, since increasing the lock range can degrade the noise immunity of the system, in a noisy environment the controller can slow down the convergence speed until locking is achieved. Once the system is in lock, the convergence speed can be increased to improve the acquisition speed. The performance of the SC-DTL system was assessed against similar arctan-based loops and the results demonstrate ...

This article proposes a time-delay digital tanlock loop (TDTL), which uses a new phase detector (PD) design that is optimised for noise reduction making it amenable for applications that require wide lock range without sacrificing the level of noise immunity. The proposed system uses an improved phase detector design which uses two phase detectors; one PD is used to optimise the noise immunity whilst the other is used to control the acquisition time of the TDTL system. Using the modified phase detector it is possible to reduce the second- and higher-order harmonics by at least 50% compared with the conventional TDTL system. The proposed system was simulated and tested using MATLAB/Simulink using frequency step inputs and inputs corrupted with varying levels of harmonic distortion. A hardware prototype of the system was implemented using a field programmable gate array (FPGA). The practical and simulation results indicate considerable improvement in the noise performance of the proposed system over the con...

This paper presents a novel implementation of the Maximally Stable Extremal Regions (MSER) detector on system-on-chip (SoC) using 65nm CMOS technology. The novel SoC was developed following the Application Specific Integrated Circuit (ASIC) design flow which significantly enhanced its realization and fabrication, and overall performances. The SoC has very low area requirement (around 0.05 mm2) and is capable of detecting both bright and dark MSERs in a single run, while computing simultaneously their associated regions' moments, simplifying its interfacing with other image algorithms (e.g. SIFT and SURF). The novel MSER SoC is power-efficient (requires 2.25 mW) and memory-efficient as it saves more than 31% of the memory space reported in the state-of-the-art MSER implementation on FPGA, making it suitable for mobile devices. With 256×256 resolution and its operating frequency of 133 MHz, the SoC is expected to have a 200 frames/second processing rate, making it suitable (when integrated with other algorithms in the system) for time-critical real-time applications such as visual surveillance.

This paper introduces a dramatically novel traffic signs recognition (TSR) system that can perform traffic sign detection and tracking simultaneously. The proposed approach utilizes intensity images and the depth images, in parallel, to robustly detect and track traffic signs in real-time. Additionally, we suggest to supplement the ordinary traffic signs with the corresponding quick-response (QR) code plates that inherent the many advantages of the QR-codes, introducing the concept of QR-TSR systems.

A major design factor for an accurate and successful DOA estimation in smart antenna systems is the appropriate choice of the antenna array configuration. This paper proposes a new array configuration called Uniform Circular Displaced Antenna Array (UC-DAA), which is especially useful for detecting coherent signals encountered in multipath environments. The proposed configuration is composed of two concentric uniform circular arrays with angular rotational separation. Numerical results show that the proposed UC-DAA configuration outperforms both uniform circular arrays (UCA) and uniform linear displaced antenna array (UL-DAA) configurations, in terms of reduced computational complexity and improved angular resolution of coherent signals without the need of spatial smoothing.

Energy detection is a favorable mechanism in several applications relating to the identification of deterministic unknown signals such as in radar systems and cognitive radio communications. The present work quantifies the detrimental effects of cascaded multipath fading on energy detection and investigates the corresponding performance capability. A novel analytic solution is firstly derived for a generic integral that involves a product of the Meijer $G-$function, the Marcum $Q-$function and arbitrary power terms. This solution is subsequently employed in the derivation of an exact closed-form expression for the average probability of detection of unknown signals over $N$*Rayleigh channels. The offered results are also extended to the case of square-law selection, which is a relatively simple and effective diversity method. It is shown that the detection performance is considerably degraded by the number of cascaded channels and that these effects can be effectively mitigated by a non-substantial increase of diversity branches., 12 pages

The increase in demand for higher functionality, smaller size, lower cost and near perpetual operation of Wireless Sensor Nodes (WSNs) are posing big challenges for system designers. A major aspect is the operational lifetime of the system which is determined by the finite energy source supplied by the battery. In WSNs, the higher power incurred due to added system functionality and the increase leakage as a result of technology scaling have high impact on the battery lifetime. In this work, memory was used to further exploit the energy efficiency at the sensor node system-level. A detailed analysis using Semi-Markov model to investigate different operational modes of WSN with the present SRAM shows an improvement of 4x at 90% duty cycle in the node's lifetime. In addition, an emerging non-volatile memory (NVM) technology, Memristor, is also explored to further improve the WSN energy efficiency. Its non-volatility nature will suppress the power wasted as leakage in SRAM during idle periods which is typical for low duty-cycle WSNs. The results show that utilizing an on-chip NVM can further improve WSN lifetime by 1x for low activity μW range sensor nodes.

This paper presents a study of the performance of the first-order time-delay digital tanlock loop (TDTL). It proposes a number of modified loop architectures that overcome some of the original TDTL design limitations. Simulation results indicate that the new architectures, which include delay switching, gain adaptation and a combination of both techniques, improve the TDTL performance in terms of acquisition speed, locking range and resilience to frequency disturbances. The first-order TDTL was also implemented on a field programmable gate array (FPGA). The real-time results from the FPGA implementation are in agreement with the ones obtained through simulation

This paper presents a new Zero-Crossing Digital Phase-Locked Loop (ZC-DPLL) for frequency synchronization and tracking. The proposed hyperbolic Σ-Δ based ZC-DPLL has an improved time jitter by a factor of 6.4 and an extended lock-in range by a factor of sinh(π)/π. These significant improvements were achieved by introducing a hyperbolic nonlinearity and a modified Σ-Δ blocks to the original ZC-DPLL architecture. These intentionally added system blocks adapt the loop filter and hence result in extending the loop locking range and improving its time jitter. The proposed hyperbolic ZC-DPLL performs well in wireless communication systems with high Doppler shift that may cause the system to lose lock. The extensive simulation results of the new architecture under various conditions show the robustness of the new architecture in terms of lock-in range, acquisition time, and jitter.

In this paper, we study the performance of a cooperative spectrum sensing (CSS) scheme over imperfect feedback channels, where N secondary users (SUs) collaborate in order to enhance the detection probability of a primary user (PU). The sensing process is divided into two phases: In the first phase each SU, which is equipped with multiple antennas, independently detect the PU signal. In the second phase, the SUs' local decisions are sent via erroneous and orthogonal feedback channels to a fusion center (FC), where a final decision is made. We utilize Bayesian criterion which accounts for the costs of misdetection and false alarm. Quasi-Newton method is employed to obtain the optimal number of antennas for a given SNR and vice versa. Our simulation results concur the mathematical derivations and validate the optimality of quasi-Newton method. We further show that the derived optimal fusion rule outperforms the OR rule, AND rule and MAJORITY rule.

This paper presents an efficient hybrid frequency synthesizer, that is capable of both integer and fractional division, design based on the Zero-Crossing Digital Phase-locked Loop architecture. The design uses an efficient adaptation mechanism to maintain the in-lock state following the division process. The fast switching, locking and acquisition of the system make it an excellent candidate for synthesis even in Doppler environment. The simulation results demonstrate that the proposed synthesizer can achieve the desired frequency division.

Recent developments in biomedical sensors has led to wearable medical devices which made energy efficiency a prime factor to consider. Hardware accelerators offer signal-processing capability with energy consumption lower than general-purpose CPUs/DSPs. Hence, great interest has risen recently in dedicated biomedical systems on chips that target extremely low levels of power consumption. Many power reduction techniques have been used, such as: multiple supply voltages (voltage islands), power gating, clock gating and voltage scaling, these techniques provided means for optimum energy efficiency operation. This paper attempts to briefly review the current research in biomedical SoCs.

Wireless sensor nodes (WSN) are used extensively to monitor a wide range of physical and environmental parameters. Data acquisition, processing, storage and transmission are mandatory requirements for different applications. These nodes are expected to generate a correct representation of the sensed quantities, which is then used to make various decisions and control actions. This means that the node requires more memory capabilities to store data either temporary or permanently. The collected data can then be used. As the monitoring device of WSN is increasingly mobile, the need for efficient power management (PM) techniques is becoming crucial in order to extend the lifetime of the battery-powered device. Energy is a critical performance metric in WSNs. Challenges facing WSN designers range from computational energy, energy consumption, energy source, communication channels, etc. A new emerging memory technology like memristor provides a good candidate for WSN PM. Memristor non-volatility features coupled with small size and low energy operation provide a normally-off instant-on mode of operation for the WSN; this will minimize the loss of energy to leakage power. The paper gives an insight about using memristor in a PM scheme at the system level.

Search and Rescue (SAR) missions for unexpected catastrophic incidents requires fast response and should provide safety especially that they lead to extreme exposure to risk of either potential victims or elements belonging to first responders team. New solutions based on robots and different techniques have been used to enhance the SAR missions in the last decade. This paper addresses a proposed solution that can be used to support collaborative teamwork between teams of robots and human in safety missions.

Wireless sensor networks (WSN) are used extensively to monitor a wide range of physical and environmental parameters. The collected data can then be used to make various decisions and control actions. The individual sensors nodes of a WSN typically consist of a processor, sensors, and transceiver. As the monitoring device of WSN is increasingly mobile, the need for efficient power management (PM) techniques is becoming crucial in order to extend the life of the battery.

This paper investigates a hybrid technique that uses a combined version of Received Signal Strength (RSS) and Direction of arrival (DOA) localization techniques. Simulation results prove that using the hybrid technique in one node increases the localization accuracy and provides the node with the capability of localizing other nodes by itself without any assistance from other nodes. The performance of the hybrid technique has been evaluated under both Additive White Gaussian Noise (AWGN) and Rayleigh channel conditions. Moreover, the study shows when to use the hybrid node, and where to place such node in a given environment to get the optimum results.

Femtocells are small base stations used to enhance cellular coverage in an indoor environment. However, dense femtocell deployments can lead to severe performance degradation. This paper adopts a new strategy to self-optimize the pilot power of femtocells by creating disjoint femtocell clusters which are managed by the chosen cluster heads (CHs). Each CH optimizes the coverage of its connected members by applying a multi-objective heuristic based on genetic algorithm. The simulation results show that the proposed approach can significantly reduce both the computational time and the data overhead compared with the centralized power optimization.

This paper applies the time-domain testing technique and compares the effectiveness of transient voltage and dynamic power supply current measurements in detecting faults in CMOS mixed-signal circuits. The voltage and supply current (iDDT) measurements are analyzed by three methods to detect the presence of a fault, and to establish which measurement achieves higher confidence in the detection. Catastrophic, soft and stuck-at single fault conditions were introduced to the circuit-under-test (CUT). The time-domain technique tests a mixed-signal CUT in a unified fashion, thereby eliminating the need to partition the CUT into separate analogue and digital modules.

Automatic Dependent Surveillance Broadcast (ADS-B) is an emerging aircraft surveillance technology with which the concept of Internet of Things (IoT) is being realized in air traffic networks. The future "e-enabled" aircrafts will be equipped with ADS-B devices in order to share precise surveillance and location data among the aircrafts, ground controllers and, possibly, other third parties. ADS-B is expected to reduce air traffic congestion and mitigate Air Traffic Control (ATC) inefficiencies significantly in shared airspace. In order to provide high accuracy and assurance for the ADS-B communications, a secure and reliable authentication mechanism is required. However, this task is challenging in that 1) using regular digital signatures, which was proposed in the literature as an authentication solution, requires management of complex Public Key Infrastructure (PKI) and 2) generating signatures for messages exchanged frequently in Aircraft-to-Ground (A2G) and Aircraft-to-Aircraft (A2A) communication modes can create a computational bottleneck easily. In this paper, we take a fresh approach to this problem by introducing a new type of online/offline identity-based signature scheme. Our scheme will resolve the PKI management issues and achieve high level of efficiency that makes possible for e-enabled aircrafts to perform frequent signing generations.

This paper presents an integrated biomedical processor system consists of a biomedical processor chip, MEMS-based ECG and oximetry-based Glucose alert sensors to achieve a non-invasive home diagnostic health monitoring system for diabetics. The biomedical processor integrates various computational engines such as FFT core, CAN severity algorithm classification and wireless interface. The chip targets extremely low power consumption to enable battery-powered operation for extended period of time. The sensors will provide non-invasive monitoring of ECG signals, and blood glucose levels alert at the same physical location on the human body. The unique sensor platform inevitably drives the SoC architecture to be wearable and less intrusive; thereby, providing patients with constant feedback on their critical health parameters.

The design of a second-order digital phase-locked loop (DPLL) based on the time-delay digital tanlock loop (TDTL) architecture is presented. The proposed design simplifies the architecture of the TDTL by eliminating the requirement for the time delay block. In addition, the system includes a controller block whose output feeds into the arctan phase detector of the proposed system so as to optimize the acquisition time and/or the lock range of the loop. The system performance evaluation results show that it is possible to selectively optimize certain parameters of the system in order to match specific application requirements.

Direction of Arrival (DOA) is one of the positioning techniques that can be used to localize the position of sensor nodes in Wireless Sensor Networks (WSNs). This paper presents a comparison between linear and circular array geometry in DOA estimation using MUltiple SIgnal Classification (MUSIC). A full analytical model for each geometry is developed and a comparative study of the performance of both array geometries is carried out. The numerical comparative study shows the advantages and drawbacks of each method under different sensor array and signal conditions. This comparison concentrates on several attributes which are noise level, beamwidth, and accuracy for localization in WSNs.

Self-optimization of coverage is an essential element for successful deployment of enterprise femtocells. This paper evaluates the performance of genetic algorithm, particle swarm and simulated annealing heuristic techniques to solve a multi-objective coverage optimization problem when a number of femtocells are deployed to jointly provide indoor coverage. This paper demonstrates the different behaviors of the proposed algorithms. The results show that genetic algorithm and particle swarm have a higher potential of solving the problem compared to simulated annealing. This is due to their faster convergence time which is an important parameter for dynamic update of femtocells.

This paper presents the architecture of a solar powered autonomous explorer. The autonomous explorer employs smart power management system to harvest its energy from the solar energy and monitors its usage in the system. Also it monitors its surrounding environment and communicates with a control base station. The explorer incorporates appropriate sensors to monitor various environmental conditions. The complete system was fully implemented as a prototype and its operation modes were verified. The system architecture is highly flexible and scalable one which enables expansion whenever the need arises.

This paper presents the architecture of a hybrid phase lock loop circuit topology for synchronizing a single-phase inverter fed from a renewable energy source such as a photovoltaic (PV) generator to the low voltage utility grid. The system uses a digital phase lock loop (DPLL) architecture, which is based on the arctan phase detector, driving a phase lock loop (PLL) to synchronize a PV generator with the grid. The proposed system has been tested by simulation using Simulink/Matlab. The test results, which are also presented, demonstrate the ability of the system to synchronize a PV inverter with the grid and to regain synchronization following a sudden change in the phase of the grid voltage.

This paper presents an integrated wireless system that helps a visually impaired person navigate within an indoor environment. The guidance process to help the person navigate uses a ZigBee wireless mesh network to localize the user and a compass to determine his/her orientation. The system uses a server to calculate an optimal path from the user's present location to the target location or item to be reached. The system receives voice commands from the visually impaired person and generates audio responses to guide the person. The mobile unit of the system is compact and requires relatively low power. Overall the system has minimal intrusion level and the results of various testing scenarios showed it was successful. The results also showed that the accuracy level depends on the available ZigBee modules within the mesh network and the particular zone.

This paper presents the architecture as well as the implementation of a system that helps blind person navigate independently within an enclosed environment such as the home. The system uses a wireless mesh network to provide the first level localization. It also incorporates additional components to provide more refined location and orientation information. Optimal path planning is done by a server that communicates wirelessly with the portable mobile unit that can be pushed by the blind person. The blind person issues commands and receives direction responses using audio signals.

This paper discusses various aspects of the design and implementation of the curriculum for three relatively closely related undergraduate engineering programs; namely communication, electronic, and computer engineering. A major distinctive feature of the programs is the emphasis on engineering projects carried out in groups and individually as well. The programs have strong technical focus and are embedded with integrated quality assurance measures, compared with conventional program structures that are offered by other institutions. The educational system is augmented with a multitude of mechanisms that enhance the teaching and learning process. The programs are accredited by both national and international bodies. The programs have proven to be very successful as graduates are well sought after by both industry and government.

This paper describes a complete framework for an end- to-end smart home monitoring and control system. The communication with all components of the system is done using a variety of wireless technologies. The system incorporates security features at both ends that prevent unauthorized access as well as assign privileges to the users. The complete prototype smart home system was implemented and it supports three main services: monitoring the status of devices, controlling their settings through configurations that are device dependent, and periodic notification of the status of devices. The prototype system has a modular structure that enables the incorporation of additional components and services.

In the proposed work, an adaptive first order zero-crossing digital phase locked loop (AZC-DPLL) for rapid acquisition, reliable locking, and independent of input signal level is designed, simulated and subsequently implemented on an FPGA based reconfigurable system. The finite state machine controller of the AZC-DPLL senses any changes in input signal frequency and amplitude level, that may cause the loop to loose lock, and accordingly adjusts the loop gain to bring the loop in lock within a few samples. Through this adaptation process, the conflicting requirement of fast acquisition and reliable locking is achieved.

In this paper, a first order TDTL system is designed, simulated and implemented on a reconfigurable FPGA system. Initially the loop was designed and simulated using Matlab/Simulink. Subsequently some novel modifications were introduced to the TDTL in order to allow an optimized reconfigurable implementation, which eases the design process and allows for dynamic parameter and design modifications. The reconfigurable TDTL was tested in real time conditions under the same operating conditions of the simulated loop. Comparison between the simulated and real time results indicate a high degree of correlation, making the loop attractive for various practical applications.

This paper presents the design of an off-chip supply current monitor for the detection of faults in analogue circuits. The emphasis is placed on the design of a monitor with minimum overhead that can be implemented to detect variations in the dynamic supply current. The design of the monitor and the results of using it to detect faults in an analogue circuit, in both simulation and physical environments, are outlined.

This paper presents the design of a unified supply current monitor for the detection of faults in analogue circuits. The emphasis is placed on the design of a monitor with minimum overhead that can be implemented to detect variations in the dynamic supply current. The design of the monitor and the results of using it to detect faults in an analogue circuit in a simulation environment are outlined.

This paper outlines the problems of testing analog circuits in general and those in a mixed-signal integrated circuit in particular. It proposes a system level testing technique based on the excitation of the circuit-under-test with a pseudo-random binary sequence and subsequent estimation of its impulse response. The fault detection capability of the test and data analysis methods are demonstrated by simulation results. It also shows a feasible test structure that can be incorporated on chip to test the analog functions.

The design, mathematical analysis, and testing results of the architecture of a new all-digital phase-locked loop system for synchronizing a voltage source DC-AC\ud single-phase inverter with the low voltage utility grid are presented. The system which is based on the time-delay digital tanlock loop was simulated using MATLAB/\ud SIMULINK and was tested by subjecting the grid voltage to various perturbations similar to those which can occur in a real power system, such as voltage sags and nonlinear distortion of the grid voltage waveform. Results indicate that even in the presence of such perturbations the system achieved and/or re-gained synchronization within 100 ms. The proposed system is all-digital and can be readily implemented using a field programmable gate array and easily embedded into a power inverter.

Smart homes are ones that have an intelligent environment that enables dynamic configuration of its devices as well as interaction with its occupants, be it while they are inside the home or remotely while outside. This paper outlines the major technologies that support the realisation of smart homes. It describes the complete architecture and design of a prototype smart home system that integrates a variety of wireless information and communication technologies with a variety of sensors and appliances. The prototype system enables an authorised user to monitor and control home devices equipped with a smart interface structure using a mobile phone. The system is embedded with authentication and verification mechanisms that provide secure end-to-end processing. The system is scalable through a flexible architecture that easily expands the portfolio of devices to be monitored and controlled.

Smart homes are intelligent environments that interact with their occupants in ways that improve their lives. This paper presents the ubiquitous pervasive technologies that will need to be integrated to realise the future vision of smart homes that have the intelligence to anticipate, predict and take decisions in a virtually autonomous manner. It also presents some of the major application areas that will benefit from the realisation of smart homes. It then discusses some of the challenges that need to be overcome in order for smart homes to become a reality and find acceptance from people across all sectors of the society.

A time-domain go/no-go testing strategy for analogue integrated circuit macros is presented. The strategy is based on exciting an analogue macro with a pseudo-random binary sequence and measuring the transient response generated at the external nodes, thereby eliminating the need for intermediate probing. Four methods of analysing the transient response data are discussed. Of these methods, the response digitisation is the most efficient.

This paper outlines the problems associated with testing analog and mixed-signal circuits. It discusses the failure modes and fault models used. It then proposes a go no go test method for analog circuits. The method is based on the excitation of the circuit-under-test with a pseudo random binary sequence and the subsequent analysis of the captured response. The fault detection capabilities of the test and data analysis method are demonstrated by applying them to a continuous time filter circuit operating in the mid-band frequency range. An initial assessment of the impact of the input test sequence length on the detectability of faults is also discussed.