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This paper describes an environment to accelerate fault simulation by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. The problems associated with fault simulation of digital circuits are explained. The proposed approach allows simulation speed-up of 40 to 500 times as compared to the state-of-the-art in software-based fault simulation. Based on the experiments, it can be concluded that it is beneficial to use emulation for circuits that require large numbers of test vectors while using simple but flexible algorithmic test vector generating circuits, e.g. built-in self-test. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents an optimized fault diagnosing procedure applicable in Built-in Self-Test environments. Instead of the known approach based on a simple bisection of patterns in pseudorandom test sequences, we propose a novel bisection procedure where the diagnostic weight of test patterns is taken into account. Another novelty is the sequential nature of the procedure which allows pruning the search space. Opposite to the classical approach which targets all failing patterns, in the proposed method not all of such patterns are needed to be used for diagnosis. This allows to trade-off the speed of diagnosis with diagnostic resolution. To improve the diagnostic resolution multiple signature analyzers are used. A method is proposed to partition a single signature analyzer into a set of multiple independent analyzers, and the algorithms are given to synthesize an optimal interface between the outputs of the circuit under test and the analyzers. The proposed method is compared with three known fault diagnosis methods: classical Binary Search based on patterns bisection, Doubling and Jumping. Experimental results demonstrate the advantages of the proposed method compared to the previous ones. [Copyright &y& Elsevier]