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The article reports on the development of Xilinx Inc.'s forthcoming Virtex 5 generation of field programmable gate array in the U.S. Semiconductor companies are shifting to 65-nanometer design rules which predict exceptional logic density and performance. The design rules showed an edge in process technology, circuit design, physical lay-out and software methodologies and equipped with engineering talent.

The article features on the new designs in field programmable gate array (FPGA) architecture developed and distributed by Actel Corp., Altera Corp., Amtel Systems Corp., Lattice Semiconductor Corp., QuickLogic Corp., Xilinx Inc., GiDEL Ltd., Nallatech, SBS Technologies Inc., and VMetro Inc..

The article presents information on low-cost programmable gate arrays. Now nothing will impede the field-programmable gate array's (FPGA) march into scores of volume applications. New architectures both lower the cost and improve functionality, enabling them to cost-effectively compete with application specific integrated circuits (ASICs). Smaller process geometries that shrink chip size go a long way toward reducing cost. But size isn't the only factor in the cost equation. Also driving the use of programmable devices is the shorter product life of many mass-market products. With ASICs, designers typically must allow for manufacturing cycle times of a month or more. Then there are the nonrecurring-engineering (NRE) costs. Programmable logic devices combat all of the above issues. These off-the-shelf parts have no significant NRE charges. If the system is designed properly, they can be updated in the field to correct system flaws or add new features. The per-chip costs might be higher than those of an ASIC, but after considering these other factors, FPGAs become a more cost-effective solution. To further the trend, all companies that offer FPGAs have developed families of low-cost devices that now target mass-market applications.

Programmable logic has become a vital part of design. This article explores the options for complex programmable logic devices and field programmable gate arrays for optimizing system performance in electronic design. Details are presented on input and output issues, capacity and memory options, hard and soft options for embedded processors, and design tools to pull the design together.

Over the last half decade, a new class of configurable application specific integrated circuits (ASIC) has made inroads by bridging the performance and cost gap between designs based on full custom ASIC and high density field programmable gate arrays (FPGA). Known as platform and structured ASICs, these system-on-a-chip solutions are some of the best aspects of custom ASIC and FPGA. As a result, designers have a quick time-to-market option that features lower development costs than ASIC and higher performance and often lower unit costs that FPGAs.

Discusses the design of field-programmable gate arrays (FPGA) from QuickLogic Corp. that combine multiple serial interfaces and logic. Configuration of the dual-ported random access memory to appear as multiple asynchronous first-in, first-out buffers; Direct circuit balancing; Division of the clock grid; Timing and interface flexibility.

Reports that advances in the complex, programmable logic devices (CPLD) have challenged field programmable gate arrays. List of CPLD manufacturers; Technique for lowering manufacturing cost of electrically erasable technology without compromising CPLD performance; Features of the Vantis MACH 5 series.

The article discusses the development of a high-performance programmable-logic platform by Velogix Inc. to keep pace with the accelerating shift of Field-programmable gate array (FPGA). Accordingly, FPGA can take on data-path-dominated designs that calls substantial computation capabilities which also allows billions of multiply-accumulate operations. The company developed the logic platform to run billions of operations in video and imaging, test and measurements and communications.

The article presents information related to Altera Corp.'s new 65-nm field programmable gate arrays. The company has launched the enhanced version of its adaptive logic module (ALM) for 65-nanometer FPUAs. The enhanced ALMs developed for the Stratix III line incorporate software configurable features. The incorporation of 65-nm process technology and configurable power in each ALM helps drive down overall power in the Stratix III line. The next Quartus II release will include support for design-space convergence.

The article reports that the next-generation field programmable gate array, which is based on 65-nanometer design rules, manufactured by Xilinx Inc., is set for sampling in the second half of 2006 in the U.S. According to Chuck Tralka, director of product marketing for Advanced Products Division, the field programmable gate array will have higher gate counts than the 90-nanometer Virtex-4 devices without consuming more power.

The article presents information on programmable-logic devices (PDL). Applications traditionally supported by high-density complex programmable-logic devices (CPLDs) and low-capacity field-programmable gate arrays (FPGA) now have another option, the MachXO series of logic devices. Developed by Lattice Semiconductor, the family brings lower cost and more features to the table. Lattice harnessed the efficiency of a logic architecture based on a lookup table and combined it with high-density, nonvolatile flash storage and distributed blocks of static memory. As a result, the MachXO devices shave cost by as much as 50 per cent per logic function. The MachXO series can handle many traditional FPGA and CPLD applications due in part to its on-chip distributed memory, a low-power sleep mode, and the ability to transparently update configuration data. Similar to the fabric in the company's XP series, the logic fabric consists of an array of programmable function units that each contains four logic slices. Each slice packs a pair of four-input lookup tables and the associated configuration SRAM. Such blocks perform logic, arithmetic, distributed RAM and distributed ROM functions.

The article discusses the Fusion mixed-signal FPGA architecture from Actel, which eliminates those components so electronic designers can implement a true single-chip system. Actel will bring this architecture to market by early next year. The Fusion architecture combines configurable analog peripherals, flash memory, and a multi-megagate FPGA fabric on a single chip. The analog functions will leverage the high-voltage transistors available as part of the embedded flash-memory process used for the FPGA configuration data storage. Based on the company's ProASIC 3 FPGA fabric, the FPGA portion of the Fusion devices will be able to deliver clock speeds of over 150 MHz on datapath logic. Soft processors such as an ARM7 32-bit CPU or an 8051 MCU can be instantiated in the logic fabric.

Introduces the EasyPath series of Spartan-3 and Virtex-4 family FPGA from Xilinx Inc. Distinct features of the product; Product offering; Usability of the device; Cost of the product.

Evaluates the Cyclone II series of field programmable gate arrays from Altera Corp.