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The analog resistive switching (RS) characteristics in 2-D polycrystalline (poly-) molybdenum disulfide (MoS2) field-effect transistors (FETs) enable new electronic devices capable of emulating biological synaptic behaviors. In 2-D poly-materials, grain boundary (GB)-induced trap states are of major significance to RS behaviors. However, there is still a lack of appropriate compact models that capture accurate physical mechanisms. Therefore, we developed a surface potential-based compact model, based on the theories of the GB energy barrier and space charge limited current (SCLC). By calibrating to experimental data of MoS2, the physical parameters are extracted, and the model explains the scaling behaviors of channel lengths and grain sizes. Due to the electric-field-induced defect redistribution, the energy barrier modulation at a single-GB (e.g., intersecting GB) quantitatively matches the reported experiments. Moreover, the possible SCLC-based RS behavior is also investigated. Furthermore, we have optimized the set/reset process and simulated the postsynaptic current (PSC) with a tunable potentiation (or depression) process, and then the gate voltage dependence and statistical effects on RS and PSC have been investigated. Thus, this model provides important devices physics insights of 2-D poly-materials and it guides device design, fabrication, and material engineering, to meet the requirements of the future neuromorphic computing application. [ABSTRACT FROM AUTHOR]

An improved simulation scheme for investigating the performance of nanoscale FETs is developed in this paper. The total current of the MOSFET consists of two main components: thermionic current above the top of barrier of the channel calculated by ballistic approach and tunneling current computed by Wentzel–Kramer–Brillouoin approximation based on a full-complex-band structure. Furthermore, to get atomic-position-based potential profile in the nanoscale device, we self-consistently solve atomic charges and potentials in the real space along and transverse in the transport direction. The device performance calculated with this model shows excellent agreement with that obtained using non-equilibrium Green’s function solver (full quantum mechanism) but by using only one-tenth of the simulation resource. Moreover, special characteristics of insulating materials integrated with advanced device structures can also be incorporated in this Poisson solver. An example based on the negative capacitance MOSFET is examined with this model, and it shows significantly improved performance than conventional MOSFET. [ABSTRACT FROM PUBLISHER]

A simple two step wet etch approach to fabricate nanowires (NWs) with a tapered source/drain (S/D) architecture is presented. Based on the unique NW architecture, gate-all-around junctionless NW FETs with sub-15-nm channel length ( $L_{{\mathrm{CH}}}$ ), NW height ( $H_{{\mathrm{NW}}}$ ), and NW width ( $W_{{\mathrm{NW}}}$ ) were realized. Despite having a large equivalent oxide thickness of $\sim 4.5$ nm, high extrinsic transconductance ( $G_{{m,{\mathrm{ ext}}}}) of 820 \mu \textS/\mu \textm was achieved at V\mathrm{ D} of 0.5 V. Due to the unique tapered S/D structure, the device realized in this paper achieved S/D series resistance ( R\mathrm {SD} ) of 275 \Omega \cdot \mu \mathrm m , which is one of the lowest among the reported 3-D InGaAs MOSFETs. [ABSTRACT FROM PUBLISHER]

We present a computational study of the device performance of graphene nanoribbon tunneling field-effect transistors (TFETs) with a heterogeneous channel. By varying the length and the energy bandgap (EG) of the heterogeneous region, the on- and off-state currents ( ION and IOFF) can be effectively optimized independently. Both semiconducting and semimetallic heterogeneous regions are studied to understand the effects of EG engineering on device behaviors. In addition, the effect of gate coverage (GC) over the heterogeneous region is also investigated. We found that device performance is greatly affected by the positioning of the gate to modify the region where band-to-band tunneling occurs. For a given ION/IOFF of eight orders, our results show that, for the semiconducting heterojunction, a higher ION can be obtained by having the gate partially covering the heterogeneous region. This is due to a combination of a short tunneling length and resonant states, which leads to an increase in carrier concentration for the tunneling mechanism. On the other hand, for the semimetallic case, a similar ION/IOFF is only attainable when the heterogeneous region is not covered by the gate. A large I \rm OFF is observed for even small GC due to the valence electrons from the source traveling to the conduction bands of the semimetallic region, enhancing the carrier transport toward the drain. Our study highlights the device design consideration required when optimizing the device performance of heterojunction TFETs. [ABSTRACT FROM PUBLISHER]

The effect of 2-D electrostatic environment on the device performance of ultimately thin-body tunneling field-effect transistors (UTB-TFETs) using graphene nanoribbons (GNRs) is investigated by varying the gate-oxide thickness and insulating material with different dielectric constants (k). Compared to Si TFETs with different body thicknesses, the atomic-layer-thick structure enhances the lateral fringing fields at the source–channel interface, resulting in a lower on-state current in GNR TFETs with high-k oxide as compared to the low-k variant of the same thickness. Low- k spacers are therefore essential to counter this effect and reap the benefits of high-k dielectrics in improving the device performance of UTB-TFETs. [ABSTRACT FROM AUTHOR]