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A method of using non‐volatile and fast ferroelectric field‐effect transistor (FeFET) devices to realize Boolean logic is proposed. First, the internal states are initialized. Then, the gate and body function as input terminals, which are used to write the states of the device, based on the voltage. Finally, the output signals can be easily read through the drain current. Of the 10 Institute of Electrical and Electronics Engineers (IEEE) standard logic gates, eight can be implemented using the proposed operation method alone and by following the definitions listed herein. Thus, to enable FeFET devices to act as functional logic gates, a simple operating method is proposed, providing substantial contributions to the development of computing in memory. The experimental results provide evidence of the efficacy of this method. [ABSTRACT FROM AUTHOR]

2D semiconductor field‐effect transistors (2D FETs) have emerged as a promising candidate for beyond‐silicon electronics applications. However, its device performance has often been limited by the metal‐2D semiconductor contact, and the non‐negligible contact resistance (RSD) not only deteriorates the on‐state current but also hinders the direct characterization of the intrinsic properties of 2D semiconductors (e.g., intrinsic charge carrier mobility, μint). Therefore, a proper extraction technique that can independently characterize the metal‐2D semiconductor contact behavior and the intrinsic properties of a 2D semiconducting layer is highly desired. In this study, a universal yet simple method is developed to accurately extract the critical parameters in 2D FETs, including characteristic temperature (To), threshold voltage (VT), RSD, and μint. The practicability of this method is extensively explored by characterizing the temperature‐dependent carrier transport behavior and the strain‐induced band structure modification in 2D semiconductors. Technology computer aided design simulation is subsequently employed to verify the precision of RSD extraction. Furthermore, the universality of the proposed method is validated by successfully implementing the extraction to various 2D semiconductors, including black phosphorus, indium selenide, molybdenum disulfide, rhenium disulfide, and tungsten disulfide with top‐ and bottom‐gated configurations. [ABSTRACT FROM AUTHOR]

In this study, we fabricated an n- type fin field-effect transistor (FinFET) and a p- type FinFET (p-FinFET) to compare their hot carrier degradation (HCD) in 14-nm technology nodes. We analyzed the HCD under different gate voltages ($\text{V}_{\text {G}}$) and found that in a 14-nm technology node, the HCD of the p- FinFET was more serious than that of the n- type FinFET (n-FinFET). In addition, as $\text{V}_{\text {G}}$ increased, the HCD mechanism of the p- FinFET changed from electron–electron scattering (EES) to multiple-vibration excitation (MVE) faster than that of the n- FinFET did; thus, a larger threshold voltage ($\text{V}_{\text {T}}$) shift was observed for the n- FinFET. When $\text{V}_{\text {G}}$ increased to $\text{V}_{\text {T}}+1.2$ V for the n- FinFET and to $\text{V}_{\text {T}} -{0.8}$ V for the p- FinFET, $\Delta \text{V}_{\text {T}}$ began to increase rapidly under hot carrier stress. The distributions of $\tau \times {(}\frac {I_{B}}{I_{D}}{)}^{-{2.7}}$ - ${I}_{D}$ for the n- FinFET and p- FinFET used in this study indicated that the mechanism of HCD changed from EES to MVE as $\text{V}_{\text {G}}$ increased. This result suggests that the p- FinFET experienced more serious HCD than did the n- FinFET because of the dominance of MVE in the p- FinFET. The HCD mechanism changed with a lower $\text{V}_{\text {G}}$ value for the p- FinFET than for the n- FinFET. Finally, HCD occurred more uniformly in the entire channel for the p- FinFET than for the n- FinFET. [ABSTRACT FROM AUTHOR]

The HfZrOx (HZO) ferroelectric material is a promising material for ferroelectric memory and is compatible with the semiconductor process for ferroelectric random access memory (FeRAM) and negative capacitance field effect transistor. However, defects often exist in the grain boundary to influence the performance or reliability of devices. In addition, uniformity between devices must be considered when they are mass-produced. Therefore, the grain size will become important in determining the performance and reliability. In this study, we use electrical measurements of current–voltage, capacitance–voltage, and polarization–voltage measurements to test high- and low-temperature deposition devices, with a transmission electron microscope (TEM) image to confirm the grain size. Finally, we propose a model to explain the phenomenon and provide a method to obtain better ferroelectric memory. [ABSTRACT FROM AUTHOR]

This paper studies a composite device composed of ferroelectric random access memory (FeRAM) and metal-oxide-semiconductor field effect transistor. The relationship between the hysteresis characteristics and VG is reported, and the on/off ratios under different writing voltages are presented. The gm–VG curve of the forward and reverse sweeping shows that under forward sweep a very clear instability appears while voltage increases. The reasons for this can be explained according to the voltage divider rule, the ID formula, and gm formula of transistors, which show that there is polarization of the ferroelectric material. Accordingly, a method is proposed to determine the critical point of the ferroelectric capacitor polarization in this 1T1C structure, which is advantageous because it identifies the appropriate reading voltage necessary for an effective program state of the 1T1C device. This method was shown in three 1T1C and three FeRAMs devices with different ferroelectric areas. Finally, this method was verified by the P–V loop of FeRAMs. [ABSTRACT FROM AUTHOR]

This letter investigates the mechanism of abnormal substrate current ($\text {I}_{\text {sub}}$) after hot carrier stress (HCS) in fin field effect transistors (FinFETs). Traditionally, after HCS, the drain current and $\text {I}_{\text {sub}}$ of the saturation region will continue to decrease. In this work, however, $\text {I}_{\text {sub}}$ first decreased and then exhibited a gradual abnormal rise. This abnormal $\text {I}_{\text {sub}}$ behavior was investigated by different measurement methods and was determined to be due to trap-assisted tunneling. This study first uses different operating voltages to prove the proposed model, then applies a variable temperature stress condition to confirm the model. Finally, a junction current measurement is used to determine the location of defect generation. [ABSTRACT FROM AUTHOR]

This work investigates the effects of HfO2 layer defects, formed by the Al atoms in the metal gate, on performance and reliability in advanced n-type metal–oxide–semiconductor field-effect transistors (n-MOSFETs) with different Al content in the gate stacks. Many groups have proposed theories (e.g., Si–H bond dissociation, trapped in high- ${k}$ defects and impact ionization) to explain the degradation mechanisms in MOSFETs, with most focusing on the dissociation of the Si-H bond at the Si/SiO2 interface and the carrier trapping in the high- $k$ layer. However, for multi- ${V}_{{\text {th}}}$ devices, experimental results indicate that the formation of defects by Al atoms in the HfO2 layer is the main reason for degradation in advanced n-MOSFETs. Therefore, we propose a mechanism to clarify the deterioration in advanced n-MOSFETs with different Al content in the gate stacks, and this mechanism is confirmed by positive bias temperature instability (PBTI), hot carrier instability (HCI), HCI power-law fitting and the gate-induced drain leakage (GIDL) measurement. [ABSTRACT FROM AUTHOR]