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The technology development, combined with chip size reductions, has significantly increased power density. Furthermore, the power limitation in portable devices has increased the importance of power consumption considerably. Approximate computing as an emerging paradigm leverages the error resiliency of applications to decrease power consumption. In this paper, we propose four approximate 4:2 compressors. We utilize the gate diffusion input to achieve significant area reduction in the proposed compressors. Afterward, we employ these compressors in the structure of Dadda multipliers. Compared to the state-of-the-art works, the proposed compressors result in, on average, 45% and 42% higher accuracy and lower area, respectively. Circuit simulations were carried out at a 32-nm carbon nanotube field-effect transistor technology node by HSPICE. The comparisons between our proposed compressors and exact compressor indicate that there has been an average improvement of 55%, 60% and 46% in the number of transistors, power consumption, and delay, respectively. In addition, the proposed multipliers were used in three image processing applications, including image multiplication, sharpening, and smoothing. The results show up to 46% and 70% improvement in the mean structure similarity index metric and peak signal-to-noise ratio compared to the state-of-the-art. [ABSTRACT FROM AUTHOR]

This paper presents an ultra-low power 3T gain-cell embedded DRAM (GC-eDRAM) cell in fin field-effect transistor (FinFET). This memory structure uses fast and low leakage FinFET transistors to improve frequent refresh issue and reduce retention power consumption. To achieve high retention time and low leakage power, we use series low power transistors in the path of data failure reducing the leakage current thanks to the stack effect. Due to the slower failure of data '1' and '0', data retention time (DRT) and thus refresh frequency improving, refresh power and retention power reduction would be achieved. The 2-kB array was simulated in FinFET sub-22 nm process nodes using HSPICE. The proposed structure at 20 nm FinFET technology demonstrates over 130× higher DRT, 70% lower static power consumption, and over 50% lower cell area than the 4T cell in 28 nm fully-depleted silicon-on-insulator (FD-SOI) technology. Additionally, it offers three orders of magnitude reduction in retention power consumption compared to 4T DRM and 4TSS cells. The proposed 3T cell provides 100–1000× higher DRT than the 4TSS cell in FinFET sub-22 nm technologies. [ABSTRACT FROM AUTHOR]

Conventional static random‐access memory (SRAM) suffers from high leakage power in advanced complementary metal‐oxide‐semiconductor nodes. Meanwhile, gain‐cell embedded dynamic random‐access memory (GC‐eDRAM) is an area‐efficient alternative to SRAM, although it requires periodic refresh cycles. In this regard, this study proposes a fin field‐effect transistor (FinFET)‐based 5T GC‐eDRAM bitcell that addresses the leakage power issue of SRAM while avoiding the bandwidth‐consuming refreshes of GC‐eDRAM. Furthermore, for the feasibility of scaling down transistors, the gain‐cell design is based on the FinFET, which overcomes short‐channel problems. The proposed 5T bitcell provides additional internal feedback relative to the 4T all‐nMOS fully depleted‐silicon on insulator (FD‐SOI) gain cell to ensure the static retention of both "1" and "0" data. The 2‐kB array was simulated by employing a 7‐nm FinFET predictive technology model (PTM) using HSPICE. The simulation results show that the proposed 5T bitcell (at 0.7 V) enables over 13× smaller data retention power and 10× area reduction compared to the 4T all‐nMOS GC‐eDRAM cell in a 28‐nm FD‐SOI technology. [ABSTRACT FROM AUTHOR]

In this paper, we propose a high-precision memristive neural network with neurons implemented by complementary metal oxide semiconductor (CMOS) inverters. Regarding the process variations in the memristors and the sensitivity of the memristive crossbar structure to these fluctuations, the read operation with repetitive pulses and feedback-based write in the memristors are used to implement the neural networks trained by the ex-situ method. Moreover, accurate modeling of the neuron circuit (CMOS inverter) and decreasing the mismatch between trained weights and the limited memristances fill the gap between simulation and implementation. To employ physical constraints based on the memristor framework during the training phase, a linear function is utilized to map the trained weights to the acceptable range of memristances after the training phase. To solve the vanishing gradient problem due to the use of the tanh function as an activation function and for better learning of the network, some measures are taken. Moreover, fin field-effect transistor (FinFET) technology is used to prevent the reduction of the accuracy of the inverter-based memristive neural networks due to the process variations. Overall, our implementation improves the speed, area, power-delay product (PDP), and mean square error (MSE) of the training stage by 91.43%, 95.06%, 48.29% and 81.64%, respectively. [ABSTRACT FROM AUTHOR]

In this paper, a SRAM cell structure which uses pMOS access transistors and predischarged bitlines is presented. By using the strained pMOS transistor technology, the degradation of the read static noise margin (SNM) at high supply voltages due to the aging, especially in the presence of symmetric stress, is suppressed. In contrast to conventional cell, the write margin of the proposed cell does not degrade considerably at low supply voltages. To assess the efficacy, the proposed cell is compared with conventional cell for two cases of unstrained and strained pMOS. A comparative study is performed using mixed mode device/circuit simulations for a gate length of 22 nm. The results show that the read SNM degradation due to the symmetric aging at the supply voltage of 1V is about 6% after three years for the proposed strained structure, while degradations are 14%, 12%, and 11% for the unstrained proposed structure, unstrained, and strained conventional structures, respectively. In addition, the proposed cell has both read and write cell sigma yields higher than six for supply voltages ranging from 1V down to 0.5V while the other structures have read or write yields less than six at the minimum supply voltage. Through some work function tuning, the cell sigma yields of the other structures reach above six for both read and write while being still lower than those of the proposed structure. [ABSTRACT FROM AUTHOR]

In this paper, we propose a robust SRAM design which is based on FinFETs. The design is performed by dynamically adjusting the back-gate voltages of pull-up transistors. For the write operation, we use an extra write driver which sets the desired back-gate voltages during this operation. This approach considerably increases the write margin. During the hold state, the back-gates are precharged to the supply voltage using an extra precharge circuit. This decreases the static power. Finally, we use nMOS switches to provide the optimum back-gate voltages during the read state. To minimize the area and power overheads, an instance of the circuitry is used for each column. The performance of the proposed technique is assessed using mixed mode device/circuit simulations for a physical gate length of 22 nm. The results show that the minimum operating voltage for six-sigma read and write yield is about 0.15 V lower than that of the recently proposed structures. In addition, the suggested SRAM shows significantly higher write margin and lower static power compared to the recently proposed structures. The minimum operating voltage of our proposed structure can be lowered down to 0.5 V through some work function tuning to balance the read and write stability. This minimum voltage is 0.1 V lower than the minimum operating voltage of the other structures with similar work function tunings. [ABSTRACT FROM AUTHOR]

In this paper, an optimal approach for the design of 6-T FinFET-based SRAM cells is proposed. The approach considers the statistical distributions of gate length and silicon thickness and their corresponding statistical correlations due to process variations. In this method, a back-gate voltage is used as the optimization knob. With the help of particle swarm optimization (PSO), the back-gate voltages that maximize the yield of the SRAM array against read, write, and access time failures are found. It will be shown that, with this method, a very high yield is achieved. [ABSTRACT FROM AUTHOR]

In this paper, a 7T SRAM cell with differential write and single ended read operations working in the near-threshold region is proposed. The structure is based on modifying a recently proposed 5T cell which uses high and low V TH transistors to improve the read and write stability. To enhance the read static noise margin (RSNM) while keeping the high write margin and low write time, an extra access transistor is used and the threshold voltages of the SRAM transistors are appropriately set. In addition, to maintain the low leakage power of the cell and increase the I on / I off ratio of its access transistors, a high V TH transistor is used in the pull down path of the cell. To assess the efficacy of the proposed cell, its characteristics are compared with those of 5T, 6T, 8T, and 9T SRAM cells. The characteristics are obtained from HSPICE simulations using 20 nm, 16 nm, 14 nm, 10 nm, and 7 nm FinFET technologies assuming a supply voltage of 500 mV. The results reveal high write and read margins, the highest I on / I off ratio, a fast write, and ultra-low leakage power in the hold “0” state for the cell. Therefore, the suggested 7T cell may be considered as one of the better design choices for both high performance and low power applications. Also, the changes of cell parameters when the temperature rises from −40 °C to 100 °C are investigated. Finally, the write margin as well as the read and hold SNMs of the cell in the presence of the process variations are studied at two supply voltages of 400 mV and 500 mV. The study shows that the proposed cell meets the required cell sigma value (6 σ ) under all conditions. [ABSTRACT FROM AUTHOR]