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In this article, a 0.7 nm thick monolayer MoS2 nanosheet gate-all-around field effect transistors (NS-GAAFETs) with conformal high- κ metal gate deposition are demonstrated. The device with 40 nm channel length exhibits a high on-state current density of ~410 μ A μ m−1 with a large on/off ratio of 6 × 108 at drain voltage = 1 V. The extracted contact resistance is 0.48 ± 0.1 kΩ μ m in monolayer MoS2 NS-GAAFETs, thereby showing the channel-dominated performance with the channel length scaling from 80 to 40 nm. The successful demonstration of device performance in this work verifies the integration potential of transition metal dichalcogenides for future logic transistor applications. [ABSTRACT FROM AUTHOR]

Carbon nanotube (CNT) field effect transistors (CNFETs) show promise for the next generation VLSI systems due to their excellent scalability, energy efficiency, and speed. However, high leakage current is a drawback of large diameter CNTs (diameter (DCNT) ≥ 1.4 nm) due to the small electronic band gap (EG) ≤ 0.6 eV and effective mass. This work investigates the on‐current and off‐current tradeoff for two populations of semiconducting‐enriched CNT with DCNT ≈ 1.0 nm displaying a simultaneous 50x improvement in minimun current (IMIN) with 2.5x degradation in contact resistance compared to DCNT ≈ 1.4 nm using a Pd side‐bonded contact. A method to enhance the performance of low‐leakage CNFETs is demonstrated using sub‐monolayer self‐aligned contact doping with 0.8 nm of MoOX, which delivers a 57% reduction in contact resistance to DCNT ≈ 1.0 nm. Robustness is verified after annealing at 200 °C for 30 min and monitoring stability across 6 months post‐fabrication with no change in electrical behaviors. [ABSTRACT FROM AUTHOR]

2D materials offer a pathway for further scaling of CMOS technology. However, for this to become a reality, both n-MOS and p-MOS should be realized, ideally with the same (standard) material. In the specific case of MoS2 field effect transistors (FETs), ambipolar transport is seldom reported, primarily due to the phenomenon of Fermi level pinning (FLP). In this study we identify the possible sources of FLP in MoS2 FETs and resolve them individually. A novel contact transfer technique is used to transfer contacts on top of MoS2 flake devices that results in a significant increase in the hole branch of the transfer characteristics as compared to conventionally fabricated contacts. We hypothesize that the pinning not only comes from the contact-MoS2 interface, but also from the MoS2-substrate interface. We confirm this by shifting to an hBN substrate which leads to a 10 fold increase in the hole current compared to the SiO2 substrate. Furthermore, we analyse MoS2 FETs of different channel thickness on three different substrates, SiO2, hBN and Al2O3, by correlating the p-branch ION/IOFF to the position of oxide defect band in these substrates. FLP from the oxide is reduced in the case of Al2O3 which enables us to observe ambipolar transport in a bilayer MoS2 FET. These results highlight that MoS2 is indeed an ambipolar material, and the absence of ambipolar transport in MoS2 FETs is strongly correlated to its dielectric environment and processing conditions. [ABSTRACT FROM AUTHOR]

2-D material FETs hold the promise of excellent gate control, but the impact of nonidealities on their performance remains poorly understood. This is because of the need, so far, to use computationally intensive nonequilibrium Green’s function (NEGF) simulations. Here, we therefore use a semiclassical model to investigate the role of nonidealities in the scaling of back-gated (BG) and top-gated (TG) monolayer MoS2 FETs. We verify the electrostatics and transport of the semiclassical model with density functional theory-based NEGF simulations and calibrate nonidealities, such as interface traps (${D}_{\textsf {it}}$) and Schottky contact barrier height ($\phi _{\textsf {SB}}$) to experimental monolayer and bilayer MoS2 FETs. We find that among the nonidealities, ${D}_{\textsf {it}}$ has the strongest subthreshold swing impact with 70 mV/dec obtainable in BG devices for a ${D}_{\textsf {it}}$ of $5\times {10}^{11}$ cm−2eV $^{-1}$ , an equivalent oxide thickness (EOT) of 1 nm, and a channel length (${L}_{\textsf {ch}}$) of 5 nm. For scaled EOT, $\phi _{\textsf {SB}}$ only strongly impacts ${I}_{ \mathrm{\scriptscriptstyle ON}}$ for the TG case, as the overlapping gate thins the Schottky barriers in the BG case. We show in TG devices that a spacer of only 5 nm results in a 1000-fold drop in ${I}_{ \mathrm{\scriptscriptstyle ON}}$ because of the nonidealities. We propose positive spacer oxide charge as a solution and show that a charge density of above 1013 cm−2 is required to fully recover the device performance. [ABSTRACT FROM AUTHOR]

Ultra-thin MoS2 film doping through surface functionalization with physically adsorbed species is of great interest due to its ability to dope the film without reduction in the carrier mobility. However, there is a need for understanding how the thickness of the MoS2 film is related to the induced surface doping for improved electrical performance. In this work, we report on the relation of MoS2 film thickness with the doping effect induced by the n-dopant adsorbate poly(vinyl-alcohol). Field effect transistors built using MoS2 films of different thicknesses were electrically characterized, and it was observed that the ION/OFF ratio after doping in thin films is more than four orders of magnitudes greater when compared with thick films. Additionally, a semi-classical model tuned with the experimental devices was used to understand the spatial distribution of charge in the channel and explain the observed behavior. From the simulation results, it was revealed that the two-dimensional carrier density induced by the adsorbate is distributed rather uniformly along the complete channel for thin films (<5.2 nm) contrary to what happens for thicker films. [ABSTRACT FROM AUTHOR]

FETs made on 2-D semiconductors, typically without degenerate doping at the contacts, have a significant Schottky junction (SJ) resistance, which complicates transistor analysis. This paper evaluates the effect of the contact resistance on the 2-D-material FET characteristics through four-terminal (4-T) resistance measurements on WSe2 FETs, which allow studying the channel and contacts characteristics separately. Apart from showing the nonnegligibility of contact resistance, this paper enables a finer understanding of commonly observed phenomena, such as transistor performance improvement with dielectric-encapsulation is observed to have a stronger effect on the contact than the channel; the resistance of the forward-biased SJ is observed to be not negligible, but comparable to that of the reverse-biased junction; at biases commonly referred to as “low-bias,” the WSe2 FET resistance could be dominated by the contacts; and pinchoff can be observed at relatively lower current levels, being related to the channel-contact resistance ratio rather than their magnitudes. In the devices where true channel pinchoff can be verified, a correlation emerges between current saturating behavior and asymmetry in the output characteristics with respect to the drain–source bias polarity, a feature that may serve as a guide toward interpreting standard FET output characteristics in 2-D materials. [ABSTRACT FROM PUBLISHER]

The impact of the scaling of the channel length on the performances of metal-oxide-semiconductor field effect transistors, based on two-dimensional (2D) channel materials, is theoretically investigated, using density functional theory combined with the non-equilibrium Green's function method. It is found that the scaling of the channel length below 10nm leads to strong device performance degradations. Our simulations reveal that this degradation is essentially due to the tunneling current flowing between the source and the drain in these aggressively scaled devices. It is shown that this electron tunneling process is modulated by the effective mass of the 2D channel material, and sets the limit of the scaling in future transistor designs. [ABSTRACT FROM AUTHOR]

Conventional junctionless (JL) multi-gate (MuG) field-effect transistors(FETs) require extremely scaled channels to deliver high on-state current with low short-channel effect related leakage. In this letter, using ultra-thin 2D materials (e.g., monolayer MoS2), we present comparison of short-channel effects in JL, and inversion-mode (IM) FETs. We show that JL FETs exhibit better sub-threshold slope (S.S.) and drain-induced-barrier-lowering (DIBL) in comparison to IM FETs due to reduced peak electric field at the junctions. But, threshold voltage (VT) roll-off with channel length downscaling is found to be significantly higher in JL FETs than IM FETs, due to higher source/drain controlled charges (dE/dx) in the channel. Further, we show that although VT roll-off in JL FETs improves by increasing the gate control, i.e., by scaling the oxide, or channel thickness, the sensitivity of threshold voltage on structural parameters is found out to be high. [ABSTRACT FROM AUTHOR]

In this paper, we benchmark the performance of monolayer and bilayer MoS2 FETs (MFETs) against various multigate (MuG) Si-FET options, such as FinFETs and lateral and vertical nanowire FETs, for a 5-nm node and beyond. We compare the performance metrics of all the device options at the ring-oscillator (RO) level, accounting for not only intrinsic and extrinsic parasitic elements but also interconnects. Using the atomistic two-band ballistic quantum transport simulations, we evaluate ON-current and intrinsic capacitances for MoS2-based devices. Furthermore, we calibrate two-band model currents with more sophisticated full-band diffusive simulations to obtain realistic performance metrics at the circuit level. We show that both the intrinsic and parasitic capacitances of a single-gate MFET are lesser than those of a double-gate (DG) MFET, resulting in 13% lesser energy consumption. A DG bilayer (DGBL) MFET shows the best performance among different MFETs. In comparison toMuG FETs, the DGBL MFET offers not only lower energy consumption but also 35%–45% lower speed. In the end, to meet the target performance, we evaluate the impact of the device current, contact resistance, and back-end-of-the-line load on the speed of RO with the DGBL MFET. [ABSTRACT FROM PUBLISHER]

We propose a bilayer graphene (BLG) tunneling field-effect-transistor (TFET) suitable for digital CMOS logic circuits. The ultimate performance limit of this structure is evaluated by solving the quantum transport equations in nonequilibrium Green’s function framework. A bandgap opening is induced in BLG using both vertical electric field and top–bottom asymmetric chemical doping. To overcome the limitations of nonabrupt p-i-n junctions using practical process methods, source/drain regions are created using work-function engineered metal-graphene contacts. We evaluate the performance of BLG-TFET by taking doping gradient due to contact induced doping into account. Our BLG-TFET exhibits a subthreshold slope as low as 35 mV/dec, and I\mathrm{{\scriptstyle ON}}/I\mathrm{{\scriptstyle OFF}} as high as 2910 for a supply voltage of 0.2 V. The proposed BLG-TFET shows promise for ultralow-power applications, particularly in low to medium speed applications. [ABSTRACT FROM AUTHOR]

2D transition metal dichalcogenide based van der Waals materials are promising candidates to realize tunnel field effect transistors (TFETs) with a steep subthreshold swing (SS) for low‐power applications. Their atomically flat, self‐passivated layers offer potentially defect free interlayer tunneling. There are still several issues that need to be addressed to experimentally achieve a steep SS, e.g., the Schottky contacts, impact of thick layers, and device architecture with respect to gate configuration. This paper resolves these challenges by experimentally demonstrating MoS2/MoTe2 TFETs and their electrical characteristics, in conjunction with ab initio simulations and surface Kelvin probe microscopy. The Schottky barrier's effect at the contact regions are isolated by fabricating individual buried gates below the contacts. Devices with different top and bottom gate configurations are produced to understand the impact of gate placement on the heterostructure characteristics. Quantum transport simulations are performed on MoS2/MoTe2 multilayer stack to evaluate the impact of multiple layers on TFET performance, effect of gate placement, and the mechanism behind indirect tunneling over the heterojunction region. This work highlights the influence of the Schottky contacts, multiple layers and the role of different gate configurations on the band‐to‐band tunneling phenomenon in 2D heterojunction TFETs. [ABSTRACT FROM AUTHOR]