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This article first introduces the research background and working principle of the TX phase alignment function of the Virtex-7 series FPGA. Then, according to the application requirements of the PCIe protocol, a design scheme for 12-channel bonding based on the GTH IP core is proposed. This solution solves the traditional High-speed serial transceivers only support up to eight channel bonding problems. The simulation results and board-level verification results of the solution show that the solution can stably achieve 12-channel bonding, and at the same time, the link bandwidth can be expanded to 1.5 times.

This article first discusses the DDR3 system calibration principle of the Virtex-7 series FPGA, analyzes the reliability of the DDR3 controller under different temperature and voltage conditions, and then proposes a solution to improve the reliability of the DDR3 controller. Simulation verification and on-board debugging test results show that this solution can effectively improve the reliability of the DDR3 system in FPGA devices under different temperature and voltage changes.

This paper first introduces the influence of process parameter fluctuation on FPGA interconnect timing. Then, according to the characteristics of FPGA architecture and the implementation method, the reason of FPGA chip yield reduction caused by interconnect timing difference is analyzed. Finally, this paper proposes a technical scheme of embedded EFUSE timing calibration, and introduces the calibration circuit. Chip test results show that the scheme can effectively control interconnect timing deviation and improve FPGA chip yield when process fluctuation is serious.

This article first introduces two implementation methods of Virtex-7 series FPGA reconfiguration, and then combines two implementation methods according to their characteristics, proposes an online upgrade solution based on FPGA reconfiguration. Finally, according to the scheme design, simulation results show that the online upgrade scheme can ensure that the FPGA chip will not cause functional failure after the online upgrade.

This article first introduces the implementation of FPGA dynamic partial reconfiguration, combined with the space radiation environment’s demand for FPGA configuration refresh, and analyzes the advantages and disadvantages of different refresh control systems. According to the understanding of the FPGA bitstream structure, this paper proposes a Self-Refresh bitstream design scheme based on FPGA dynamic partial reconfiguration and designs the corresponding bitstream. The simulation results show that the bitstream design scheme is easy to implement in FPGA and significantly reduces the refresh time.

The matched-filter is widely used in real time signal processing, especially in radar signal processing. This paper presents a novel structure of a digital tracking radar matched-filter, whose hardware overhead is one third of the traditional design but its throughput is doubled. With block-floating-point arithmetic, the precision is highly improved. The whole digital matched-filter is implemented in just one FPGA chip. This ASIC has two work modes: 512 points pulse compression and 256 points pulse compression. It complements three channels of 512 points complex signals in 102 /spl mu/s. The signal-to-noise ratio formula of this matched-filter is deduced at the end of the paper.