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This paper investigates the n-type vertical slit FET (VeSFET) performance at 7-nm node and beyond by TCAD simulation. VeSFET is a twin-gate device with 3-D monolithic integration-friendly vertical terminals and horizontal channel manufactured based on SOI wafer with conventional CMOS fabrication hardware. The second gate provides the capability of transistor behavior adjustment and the potential for advanced circuit designs. The results show that VeSFET can provide high I {\mathrm {eff}} to I {\mathrm {off}} ratio, low gate capacitance, high \Delta V {t}/ V { {\textit{g2s}}} , and competitive drive capability with respect to a reference FinFET of comparable dimensions. [ABSTRACT FROM PUBLISHER]

An analytical model of parasitic capacitancein inserted-oxide FinFETs (iFinFETs) is proposed. A comparative study on the parasitic capacitance of contemporary multigate devices conforming to 7-nm technology node targets is presented. The proposed model is validated against 3-D Technology Computer-Aided Design (TCAD) simulations. Dependence of the iFinFET parasitic capacitance on device design parameters, such as the inserted-oxide thickness (Tiox) and inserted-oxide recess (Trec), is shown using the proposed model and TCAD simulations. [ABSTRACT FROM AUTHOR]