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A dual-bit trapping device, which solves most of the problems by using a split-gate structure, inspired by the HIMOS concept is presented. The device allows a high density thanks to dual-bit/cell storage and it is easily scalable since the structure is fully self-aligned and the bit areas are physically isolated.

This article discusses the materials aspects involved in the successful integration of hybrid floating gate (HFG) devices for NAND applications. In HFG, a Si(n type)\metal(p type) stack replaces the standard poly-Si FG. The high work function metal helps to enlarge the program window by limiting the leakage through the high- k intergate dielectric (IGD); the use of high- k IGD enables to scale the equivalent oxide thickness (EOT) of the HFG cell. Our recent progresses in the understanding of the materials characteristics (IGD crystallinity and HFG-IGD thermal stability) that influence memory performance have allowed to demonstrate that HFG can be a solution to scale planar flash beyond the 20 nm node with the best preferable hybrid floating gate structure being a Ru-based HFG and a 3-layers IGD stack of HfAlO\Al2O3\HfAlO. Indeed, through the correct selection and combination of materials for process conditions that are relevant in flash memory fabrication flows, we will show that program windows can be suitably engineered. Finally, the materials challenges for keeping acceptable memory retention characteristics are also highlighted. [ABSTRACT FROM AUTHOR]

The required transition from control gate wraparound to planar structure for NAND flash scaling below 20-nm node causes important loss of coupling factor. In order to recover the program/erase (P/E) window, we develop a novel intergate dielectric (IGD) stack. Simulations identify an ideal three-layer structure that reduces leakage through the IGD and thus improves the memory window at controlled equivalent oxide thickness. A thorough materials investigation allowed to fabricate such three-layer IGD stacks, demonstrating more than 18 V P/E window, good retention, and endurance. [ABSTRACT FROM AUTHOR]

High density of electron trapping in high- \kappa intergate dielectric (IGD) materials remains a major concern for planar memory cells with either poly-Si or hybrid floating gates (FGs). In this paper, for the first time, using the ultrafast I{-}V measurements, it is demonstrated that a significant portion of the P/E windows are actually contributed by electrons trapped initially in the high- \kappa$ IGD stacks during program/erase, and then discharged to FG or control gate during verification. More importantly, it is demonstrated, for the first time, that this fast charge transition can be suppressed using novel multilayer high- $\kappa$ IGD structures, and the fast window instability can be eliminated. [ABSTRACT FROM PUBLISHER]

High-\kappa stacks have been used in the 20-nm generation of floating gate (FG) flash memory cells as the interpoly dielectric (IPD). However, electron trapping in high-\kappa materials remains a major concern for the further development of FG technology. For conventional FG cells, read/pass disturbance in the erased states is a major issue. In this paper, for the first time, it is observed that electron trapping/detrapping in the high-\kappa IPD layers can cause severe abnormal read/pass disturbances in the programmed states. Extensive evidence shows that this instability in programmed states originates from several competing mechanisms, including the redistribution of electron trapping between the IPD and FG and the electron discharging from FG/IPD into the control gate. This issue should be addressed in the development of future generations of FG Flash technology with higher-\kappa IPD materials. [ABSTRACT FROM PUBLISHER]

Abstract: The only way to keep pace with Moore’s Law is to use probabilistic computing for memory design. Probabilistic computing is ‘unavoidable’, especially when scaled memory dimensions go down to the levels where variability takes over. In order to print features below 20nm, novel lithographies such as Extreme Ultra Violet (EUV) are required. However, transistor structures and memory arrays are strongly affected by pattern roughness caused by the randomness of such lithography, leading to variability induced data errors in the memory read-out. This paper demonstrates a probabilistic–holistic look at how to handle bit errors of NAND Flash memory and trades-off between lithography processes and error-correcting codes to ensure the data integrity. [Copyright &y& Elsevier]

Abstract: The main reliability issue of highly scaled floating gate NAND Flash memories is the cross-cell interference phenomenon. This is an active area of research in microelectronics engineering. In the last decade, there has been much progress and there are already proposed models for extraction of parasitic capacitive couplings within floating gate transistors. However, most of simulation-based methodologies for evaluation of the impact of cross-cell interference on the electrical behavior rely on deterministic capacitive coupling, neglecting the variability effects. This approach ignores the variable nature of the capacitive couplings caused by technological limitations such as line edge roughness (LER) in advanced technological nodes. The aim of this work is to present an alternative approach of modeling threshold voltage disturbance propagation in a raw NAND Flash memory array, sourced by variability-affected parasitic capacitive couplings. The major contribution of this work is the introduction of probabilistic framework to link the process technology and system level. [Copyright &y& Elsevier]

A fast response technique is developed to investigate the short-term postprogram and post-erase discharge in Flash memory devices. The procedure is based on fast VTH -evaluation methods developed for bias temperature instability and provides the transient characteristics after 20 ms under the program or erase conditions. The following different structures are investigated: 1) \SiO2/high-k stacks; 2) charge trap memories; 3) and floating gate memories. Dielectrics targeted for Flash memory applications are used as charge trap layers and interpoly dielectrics. In this paper, we show results on \Al2\O3, DyScO, GdScO, and hexagonal and perovskite LuAlO. The postprogram and post-erase curves hold useful information about the dielectric properties and are used as a fast screening technique for alternative materials. [ABSTRACT FROM PUBLISHER]

The capacitive coupling interference within floating-gate transistors is the main scaling barrier for highly dense nand Flash memories. In this case study, we propose a simulation-based methodology for the variability modeling, which is caused by line edge roughness in advanced technological nodes. The aim of this work is to present the approach by modeling the threshold voltage disturbance propagation mechanism in a raw memory array, caused by the variability-affected parasitic coupling. The variability aware model is statistically designed for evaluation of the cell-to-cell interference variability impact on disturbances of threshold voltage and the error generation in a 16-nm half-pitch nand Flash memory. [ABSTRACT FROM PUBLISHER]