Search

Self-heating effects (SHEs) were investigated through simulations for 3-D V- NAND flash memory. The SHEs are varied by adjusting the thickness of the poly-crystalline channel, the number of stacked cells along with a bitline, and the configuration of the multilevel cell. The simulation data show that the temperature change was smaller than 3 K under read operation; therefore, SHEs are no longer a concern for advances in 3-D V- NAND flash memory technology. In addition, we investigated whether SHEs are influenced by a thermally isolated channel, as in a novel architecture named peripheral-under-cell (PUC), which is a peripheral circuit under cell for 3-D V- NAND flash memory. [ABSTRACT FROM AUTHOR]

High-pressure (HP) deuterium (D2) annealing was applied to a gate-all-around (GAA) MOSFET to improve device reliability and memory performance. The structure had gate dielectrics of oxide–nitride–oxide (ONO), which completely straddled vertically stacked multiple silicon nanowires (Si-NWs) with n+ poly-Si gates. The HP D2 annealing was effective for the vertically stacked GAA MOSFET as it was for a conventional planar MOSFET. In addition, the resistance of the n+ poly-Si gate was also reduced after the HP D2 annealing. This is attributed to the passivation of defects among adjacent poly-Si grains by the HP D2. The reduced gate resistance (RG) is advantageous for decreasing RC delay. Direct characterizations of dc I – V and analyses of ac low-frequency noise (LFN) supported the abovementioned behaviors. [ABSTRACT FROM AUTHOR]

Self-heating effects (SHEs) in 3-D V-NAND flash memory are investigated using simulations. First, temperature increase is estimated during the read operation, and a hot spot region along the bit-line is identified. Then, a novel bilayered macaroni filler is proposed to relieve the SHEs. A highly thermally conductive layer is plugged into the macaroni oxide filler as a heat sink. The heat dissipation efficiency is improved by up to 21% in the proposed structure. As a result, the reliability issues induced by SHEs can be avoided in V-NAND flash. [ABSTRACT FROM AUTHOR]

An erasing method capable of speeds 104-fold faster compared with those by the conventional Fowler–Nordheim (FN) erasing technique is experimentally demonstrated in a gate-all-around junctionless (JL) charge-trap flash memory device using thermal excitation with the aid of electric field. A gate electrode serving as a built-in heater generates Joule heat for thermal excitation of trapped electrons in the charge-trap layer. The electrons excited by thermal excitation are further accelerated for injection into the silicon body by an in-situ applied E-field between the gate and the JL body. Hence, the trapped electrons are removed within 70 ns by electro-thermal erasing. [ABSTRACT FROM AUTHOR]

Abstract Irrecoverable data destruction on a mobile device is important to prevent unintentional data disclosure. In this regard, transient electronics, a form of electronics that can be made to disappear or can be destroyed in a controllable manner, has been actively researched. To erase data completely, irreversible reactions such as physical or chemical destruction have been used. However, these techniques either require external voltage or destroy a memory device so that it cannot be reused. Here, we demonstrate a novel self-powered data-erasing method for nanoscale flash memory devices which uses triboelectricity via a kill switch, which consists of a nylon pad connected to a gate electrode of the flash memory. Through a one-time touch of the kill switch by a finger wearing a polytetrafluoroethylene (PTFE) glove, data stored in flash memory is set to the ‘1′ state on the chip scale simultaneously with low-level triboelectricity, allowing the memory to be reused afterward. Moreover, the memory can be permanently destroyed by a single touch of the kill switch with a finger without a glove that generates high-level triboelectricity. These erase methods provide a rapid and convenient means of self-powered irrecoverable data erasing in the era of the Internet of Things (IoT). Graphical abstract fx1 Highlights • First demonstration of data erasing for a silicon-based flash memory without external voltage using triboelectricity. • A memory state of the nanoscale flash memory is changed from a program state to the erase state when triboelectricity is induced to a gate electrode. • This triboelectric data erasing without external power supply is 106-fold faster than a conventional erasing method with external power supply. • First demonstration of two-level data-erasing that offers both reusable erasing and permanent destruction against threatening of hacking. • This triboelectric data erasing is applicable to commercial silicon-based flash memory, which has been used for solid-state drive (SSD) and USB memory. [ABSTRACT FROM AUTHOR]

In this study, a thermal method for erasing and permanently destroying data stored in flash memory fabricated on a suspended silicon nanowire is demonstrated. An intentionally applied heat treatment is used to erase the data stored in the charge trap layer of the flash memory. The data destruction is verified and analyzed at a unit cell level as well as in a commercial off-theshelf chip. Characteristics of memory performance and reliability are also investigated. Then, the feasibility of the proposed method is further evaluated for next generation 3-dimensional V-NAND. [ABSTRACT FROM AUTHOR]