Search

This paper presents and analyzes a heterogeneous implementation of an industrial use case based on K-means that targets symmetric multiprocessing (SMP), GPUs and FPGAs. We present how the application can be optimized from an algorithmic point of view and how this optimization performs on two heterogeneous platforms. The presented implementation relies on the OmpSs programming model, which introduces a simplified pragma-based syntax for the communication between the main processor and the accelerators. Performance improvement can be achieved by the programmer explicitly specifying the data memory accesses or copies. As expected, the newer SMP+GPU system studied is more powerful than the older SMP+FPGA system. However the latter is enough to fulfill the requirements of our use case and we show that uses less energy when considering only the active power of the execution. This work is partially supported by the European Union H2020 project AXIOM (grant agreement n. 645496), HiPEAC (grant agreement n. 687698), and Mont-Blanc (grant agreements n. 288777, 610402 and 671697), the Spanish Government Programa Severo Ochoa (SEV-2015-0493), the Spanish Ministry of Science and Technology (TIN2015- 65316-P) and the Departament d’Innovació, Universitats i Empresa de la Generalitat de Catalunya, under project MPEXPAR: Models de Programaci´o i Entorns d’Execució Paral·lels (2014-SGR-1051).

High-Performance Computing can be accelerated using long-vector architectures. However, creating efficient coding implementations for these architectures can be challenging. This Master's thesis focuses on implementing four well-known and widely-used graph processing algorithms using the RISC-V Vector Extension, leveraging an experimental system in an FPGA. I present a graph storage format that benefits from long vectors and describe how these four algorithms can be rewritten to utilize it. This thesis also introduces an instrumentation tool for FPGA that I developed to link the output of electrical engineering software with performance analysis tools for HPC. This tool allows users to visualize information coming from the logic analyzer internal to the FPGA with powerful visualization tools, permitting fine-grain analysis of the FPGA signals correlated with the code running on it. This tool has been integrated into the experimental performance analysis tools of BSC. In this thesis I leverage this tool to analyze and improve my implementations of graph algorithms for long-vector architectures, collecting the process and thoughts behind each optimization. Finally, I compare the performance of my vector implementations with other machines, such as the NEC SX-Aurora, a commercial RISC-V board, and an Intel chip.

En el món del "High-Performance Computing", el processador és essencial. Recentment, Europa està fent grans esforços en promoure tecnologia europea. La "European Processor Initiative" sorgeix d'aquest esforç. Com a part de la iniciativa, múltiples processadors estan sent dissenyats. Alguns implementant l'arquitectura "RISC-V", una "ISA" "open-source". Al llarg del desenvolupament del processador, disposar d'eines és fonamental per facilitar el testatge i automatitzar tasques. Aquest treball final de grau es focalitza en millorar una "pipeline" de "Continuous integration" emprada per detectar errors en un entorn Linux i en una "Field Programmable Gate Array (FPGA)" emulant un comportament d'usuari final. In the High-Performance Computing world, the processor is essential. In recent years, Europe has devoted a lot of effort into promoting European technology. The European Processor Initiative stems from this effort. As part of the initiative, multiple processors are being developed. Some implementing the RISC-V architecture, an open-source ISA. During the development of a processor, tools are fundamental to ease testing and automatize tasks. This final degree project focuses on improving a Continuos Integration pipeline used to detect bugs in an Field Programmable Gate Array (FPGA) and Linux environments emulating final user behaviour.

Acceleration is a widely used technique in the field of High-Performance Computing (HPC) to improve the performance of standard CPU powered computational nodes. Examples of widely used accelerators in HPC are graphic cards (\textit{e.g.}, Nvidia GP-GPU) and vector accelerators (\textit{e.g.}, NEC Aurora-SX). Custom acceleration is often achieved using FPGAs. One of the challenges of adopting FPGA-based accelerators in HPC is their programmability. OmpSs@FPGA is a programming model developed at the Barcelona Supercomputing Center (BSC) that allows adding FPGA acceleration to an application in an easy and device-independent way. In this project, we used OmpSs@FPGA to accelerate in hardware the generation of random numbers. Monte Carlo algorithms are widely used in scientific applications in the context of HPC. These algorithms are characterized by its need of random number input. It is possible to offload random number generation using hardware acceleration techniques. We implemented three different versions of a linear-feedback shift register (LFSR) random number generator: a CPU-only version and two OmpSs@FPGA accelerated versions. The performance of the three implementations has been evaluated in the context of the Ising model with the Metropolis algorithm, which belongs to the family of Monte Carlo methods used in statistical physics. This provides a real world use case that makes heavy use of pseudorandom number generation. While we verified that the Ising model is indeed limited by the generation of random numbers, our results show that the acceleration of random number generation using FPGA needs to be carefully deployed. Our preliminary results show a high dependency between the achieved performance and the overhead introduced by the offloading infrastrcture. L'acceleració hardware és una tècnica àmpliament utilitzada en el camp de la computació d'alt rendiment (HPC) per augmentar el rendiment dels nodes de càlcul estàndard basats en CPU. Alguns exemples d'acceleradors d'ús comú en HPC poden ser les targetes gràfiques (p. ex. Nvidia GP-GPU) o els acceleradors vectorials (p. ex. NEC Aurora-SX). L'acceleració especialitzada es pot obtenir amb FPGAs. Una de les dificultats que limiten l'ús dels acceleradors FPGA en el món del HPC és la seva programabilitat. OmpSs@FPGA és un model de programació desenvolupat al Barcelona Supercomputing Center (BSC) que permet incorporar acceleració FPGA a una aplicació de manera fàcil. En aquest projecte, hem utilitzat OmpSs@FPGA per accelerar en hardware la generació de nombres aleatoris. Els algoritmes Monte Carlo s'utilitzen àmpliament en aplicacions científiques i HPC. Es caracteritzen per la necessitat de nombres aleatoris per al seu funcionament. És possible aplicar offloading a la generació de nombres aleatoris mitjançant acceleració hardware. Hem implementat tres versions d'un generador de nombres aleatoris basat en LFSR: una versió CPU-only i dues versions accelerades amb OmpSs@FPGA. El rendiment de les tres implementacions s'ha avaluat en el context del model d'Ising amb l'algoritme de Metropolis, que pertany a la família dels algoritmes Monte Carlo utilitzats en el camp de la física estadística. Això ens proporciona un cas d'ús real que en fa un ús intensiu de la generació de nombres aleatoris. Tot i haver verificat que el model d'Ising queda limitat per la generació de nombres aleatoris, els resultats obtinguts mostren que la generació de nombres aleatoris accelerada amb FPGA s'ha d'implementar amb cura. Els nostres resultats preliminars presenten una forta dependència entre el rendiment obtingut i l'overhead introduït per la infraestructura d'offloading

The thesis evaluates the current state-of-the-art of RISC architectures in HPC. Studying the performance, power, and energy to solution in heterogeneous SoCs. For the evaluation 2 arm platforms (CPU+GPU, CPU+FPGA), 1 RISC-V platform and 1 Open Source RISC-V core running in an FPGA have been tested.