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Advanced front-end readout chips for medium and high energy nuclear physics experiments have shown an increasing trend towards digitization in recent years, increasing system integration and reducing power consumption. Guided by critical scientific goals, the Institute of Modern Physics of the Chinese Academy of Sciences is building a central scientific installation termed as the high intensity heavy-ion accelerator facility (HIAF). HIAF fragment separator (HFRS) is an important experimental device for radioactive beam physics research on the HIAF. The characteristics of HFRS strong current and the readout demand of the large area detectors put forward the requirements of high-count rate, high integration, and high time resolution for the front-end readout electronics, and therefore the development of the advanced digital front-end readout chip is urgently needed. The paper developed a high-count rate multi-channel time measurement and serial readout circuit (HMTRC) based on 180 nm complementary metal oxide semiconductor (CMOS) process, which can accelerate the development and iteration of such digital front-end readout chips. The HMTRC has now been integrated into a self-developed 16 channel digital-analogue hybrid front-end readout chip, EDIMS, for position sensitive detectors on HFRS. When a charge signal is input, the charge-sensitive amplifier (CSA) integrates the signal into an exponentially decaying voltage signal and fans out to the time path and the energy path. In the time path, the fast shaper inputs the output signal of the CSA into the discriminator after shaping, and outputs the self-triggering signal after comparing with the threshold. The digital first input first output (FIFO) memory in each channel records information such as the timestamp and channel number corresponding to the front time of the trigger signal. In the energy path, the slow shaper integrates the output signal of the CSA into a quasi-Gaussian signal. The output signal of the peak detect and hold circuit (PDH) follows the leading edge of the output signal of the slow shaper to detect and maintain peak energy information. The analog memory based on switched-capacitor arrays stores the information. The polling readout module based on the token ring logic reads out the stored charge and time information periodically and synchronously, which has advantages in the de-sparsification and de-randomization of nuclear events and the improvement of peak count rate. The chip has been fabricated and the HMTRC has a size of 535 μm×930 μm and a power consumption of 32.31 mW. The laboratory test system consists of a chip test board, a XILINX Kintex-7 development board, a host computer, a signal generator and an oscilloscope. The field programmable gate array (FPGA) on the development board provides the master clock and control signals for the chip under test. The output data from the chip are transferred to the development board by a high-speed connector, packaged by cache processing and uploaded to the host computer via the integrated logic analyzer for analysis. The test results show that the function of the HMTRC and the coarse time of the timestamps are in line with expectations, but the fine time of timestamp between each channel is different, and there is some error compared with the theoretical value. The test results also show that the accuracy of time resolution is better than 2 ns, which is as expected, and basically meets the requirements of the application. The next version of the design will optimize the inconsistency between the channels and fine time error of the timestamp, and add the inter-integrated circuit (I2C) or the serial peripheral interface (SPI) slow control module to improve the versatility of this circuit.

The Majorana Demonstrator comprises two arrays of high-purity germanium detectors constructed to search for neutrinoless double-beta decay in 76Ge and other physics beyond the Standard Model. Its readout electronics were designed to have low electronic noise, and radioactive backgrounds were minimized by using low-mass components and low-radioactivity materials near the detectors. This paper provides a description of all components of the Majorana Demonstrator readout electronics, spanning the front-end electronics and internal cabling, back-end electronics, digitizer, and power supplies, along with the grounding scheme. The spectroscopic performance achieved with these readout electronics is also demonstrated.

To search for dark matter candidates with masses below O (MeV), the SPLENDOR (Search for Particles of Light dark mattEr with Narrow-gap semiconDuctORs) experiment is developing novel narrow-bandgap semiconductors with electronic bandgaps on the order of 1–100 meV. In order to detect the charge signal produced by scattering or absorption events, SPLENDOR has designed a two-stage cryogenic HEMT-based amplifier with an estimated charge resolution approaching the single-electron level. A low-capacitance (∼ 1.6 pF) HEMT is used as a buffer stage at T = 10 mK to mitigate effects of stray capacitance at the input. The buffered signal is then amplified by a higher-capacitance (∼ 200 pF) HEMT amplifier stage at T = 4 K. Importantly, the design of this amplifier makes it usable with any insulating material—allowing for rapid prototyping of a variety of novel detector materials. We present the two-stage cryogenic amplifier design, preliminary voltage noise performance, and estimated charge resolution of 7.2 electrons. [ABSTRACT FROM AUTHOR]

For the Phase-II Upgrade of the ATLAS Detector [1], its Inner Detector, consisting of silicon pixel, silicon strip and transition radiation sub-detectors, will be replaced with an all new 100% silicon tracker, composed of a pixel tracker at inner radii and a strip tracker at outer radii. The future ATLAS strip tracker will include 11,000 silicon sensor modules in the central region (barrel) and 7,000 modules in the forward region (end-caps), which are foreseen to be constructed over a period of 3.5 years. The construction of each module consists of a series of assembly and quality control steps, which were engineered to be identical for all production sites. In order to develop the tooling and procedures for assembly and testing of these modules, two series of major prototyping programs were conducted: An early program using readout chips designed using a 250 nm fabrication process (ABCN-250) [2,2] and a subsequent program using a follow-up chip set made using 130 nm processing (ABC130 and HCC130 chips). This second generation of readout chips was used for an extensive prototyping program that produced around 100 barrel-type modules and contributed significantly to the development of the final module layout. This paper gives an overview of the components used in ABC130 barrel modules, their assembly procedure and findings resulting from their tests.

Conventional CMOS technology operated in cryogenic conditions has recently attracted interest for its use in low-noise electronics. We present one of the first characterizations of 180 nm CMOS technology at a temperature of 100 mK, extracting I/V characteristics, threshold voltages, and transconductance values, as well as observing their temperature dependence. We find that CMOS devices remain fully operational down to these temperatures, although we observe hysteresis effects in some devices. The measurements described in this paper can be used to inform the future design of CMOS devices intended to be operated in this deep cryogenic regime.

The low-noise operation of readout electronics in a liquid argon time projection chamber (LArTPC) is critical to properly extract the distribution of ionization charge deposited on the wire planes of the TPC, especially for the induction planes. This paper describes the characteristics and mitigation of the observed noise in the MicroBooNE detector. The MicroBooNE's single-phase LArTPC comprises two induction planes and one collection sense wire plane with a total of 8256 wires. Current induced on each TPC wire is amplified and shaped by custom low-power, low-noise ASICs immersed in the liquid argon. The digitization of the signal waveform occurs outside the cryostat. Using data from the first year of MicroBooNE operations, several excess noise sources in the TPC were identified and mitigated. The residual equivalent noise charge (ENC) after noise filtering varies with wire length and is found to be below 400 electrons for the longest wires (4.7 m). The response is consistent with the cold electronics design expectations and is found to be stable with time and uniform over the functioning channels. This noise level is significantly lower than previous experiments utilizing warm front-end electronics.

Owing to a change in the scope of physics research, the AMBER spectrometer at CERN is undergoing an update on its instrumentation and trigger strategy for the data acquisition system. One of the key updates is the adoption of a free-running and trigger-less operation, which differs from the predecessor of AMBER, COMPASS, by working in a continuous mode but in an event-based triggered way. In this article, we present a multichannel data-acquisition platform developed in line with the next generation of trigger-less and free-running data acquisition systems. The platform is based on a pre-existing Mezzanine Sampling ADC board for the analog-to-digital conversion and a Xilinx Zynq Ultrascale+ System on Module for online real-time data processing. We also present the evaluation of the system operating in continuous mode, taking data from a 25-element electromagnetic calorimeter prototype with a muon beam, during the first AMBER pilot run. The acquired data were used for noise and pulse shape studies required for the design of the algorithms for lossless compression and data feature extraction needed for trigger-less operation. [ABSTRACT FROM AUTHOR]

We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Potential design improvements to address the resolution drift and tails are discussed.

We present the measured baseline ionization resolution of a HEMT-based cryogenic charge amplifier coupled to a CDMS-II detector. The amplifier has been developed to allow massive semiconductor dark matter detectors to retain background discrimination at the low recoil energies produced by low-mass WIMPs. We find a calibrated baseline ionization resolution of σ E = 91 eV e e. To our knowledge, this is the best direct ionization resolution achieved with such massive (≈ 150 pF capacitance) radiation detectors. [ABSTRACT FROM AUTHOR]

Abstract The LAB4D is a new application-specific integrated circuit (ASIC) of the Large Analog Bandwidth Recorder and Digitizer with Ordered Readout (LABRADOR) family, for use in direct wideband radio frequency digitization such as is used in ultrahigh energy neutrino and cosmic ray astrophysics. The LAB4D is a single channel switched-capacitor array (SCA) 12-bit sampler with integrated analog-to-digital converters (ADC), developed in the TSMC 0.25 µm process. The LAB4D, operating at 3. 2 GSa ∕ s , contains 4096 total samples arranged in 32 windows, for a total record length of 1280 ns. The 3 dB bandwidth is approximately 1.3 GHz, with a directly-coupled 50 Ω input. This represents a factor of 16 increase in the sample depth and an increase in analog bandwidth in comparison to the previous generation (LAB3) digitizer. Individually addressable windows allow for sampling and digitization to occur simultaneously, leading to nearly dead time-free kHz readout rates. All biases and current references are generated via internal digital-to-analog converters (DACs), resulting in a digitizer that requires minimal support circuitry. In addition, the LAB4D contains sample cell timebase trimming capabilities, reducing the intrinsic sample-to-sample time variance to less than 5 ps, an improvement of about 80%. This feature allows the LAB4D to be used in precision timing applications and reduces post-hoc calibration requirements. [ABSTRACT FROM AUTHOR]

Abstract The Thin-TOF PET (TT-PET) project aims at the construction of a small-animal PET scanner based on silicon monolithic pixel sensors with 30 ps time resolution for 511 keV photons, equivalent to 100 ps time resolution for minimum ionizing particles. The high time resolution of the pixel sensor allows for precise time of flight measurement of the two photons and a significant improvement in the signal-to-noise ratio of images. The TT-PET scanner also has sensitivity for photon depth of interaction, thus improving the spatial resolution across the whole view of the scanner. The performance of the scanner estimated by a GEANT4 Monte Carlo simulation is presented. In order to achieve the high time resolution, the SiGe heterojunction bipolar transistor technology (SG13S from IHP) was chosen for fast integration, low equivalent noise charge and low power consumption. TCAD simulations were used to design the appropriate guard rings for the pixel sensor. Laboratory measurements of the first test chip show the correct functionality of the guard ring up to a bias potential of 200 V applied to the pixels and a good signal-to-noise ratio for the detection of electrons from a 90Sr source. A test beam measurement with an un-thinned chip shows more than 99 % efficiency and approximately 200 ps time resolution for minimum ionizing particles despite the absence of wafer thinning and post-processing. Highlights • The Thin-TOF PET (TT-PET) project aims at the construction of a TOF PET scanner. • The robustness of the first prototype against breakdown up to a potential 160 V. • First prototype shows a time resolution of 200 ps for MIPs under a test beam. [ABSTRACT FROM AUTHOR]

Abstract Array optical transceiver provides high speed data transmission with low mass fibers for detector readout in collider experiments. The module assembly in miniature form factor is favorable for compactness in applications. We report on investigation for components and chip-on-board assembly of an array transmitter with an optical interface of about 2 mm in height suitable for 10+ Gbps/ch data transmission in a radiation hazard environment. The active opto-electronics of 850 nm GaAs VCSELs are investigated for ageing in burn-in at 85°C, 85% RH condition. A radiation-tolerant laser driver is developed in 65 nm CMOS technology. The module assembly includes the VCSEL aligned to optical path component for light coupling to multi-mode fibers. The tolerance of optical path component in radiation is tested in Co60 gamma-ray of up to 300 kGy. The light coupling efficiency is examined for VCSEL emission modes in far-field distributions. [ABSTRACT FROM AUTHOR]

Abstract A serializer ASIC and a VCSEL driver ASIC are needed for the ATLAS liquid argon calorimeter readout phase-I upgrade. The baseline ASICs are the serializer LOCx2 and the VCSEL driver LOCld, designed in a 0.25- μ m Silicon-on-Sapphire (SoS) CMOS technology. Based on a 130-nm CMOS technology, we design two pin-to-pin-compatible backup ASICs, LOCx2-130 and LOCld-130. Their power consumptions are much lower then their counterparts. We present the design of LOCx2-130 and LOCld-130. The test results of LOCx2-130 are also presented. Highlights • We present a serializer ASIC, LOCx2-130, and a VCSEL driver ASIC, LOCld-130, for the ATLAS Liquid Argon Calorimeter trigger upgrade. • LOCx2-130 consists of two serializer channels and each channel encodes ADC data and transmits serial data at 4.8 Gbps with a latency of less than 40.7 ns. The power consumption of LOCx2-130 is about 440 mW. • LOCld-130 is a dual-channel VCSEL driver ASIC and each channel works up to 5.12 Gbps. The total power consumption of LOCld-130 is 112 mW (56 mW/channel) including the VCSELs. • Both chips meet the requirements of the ATLAS Liquid Argon Calorimeter trigger upgrade and the power consumptions are much lower than the previous version. [ABSTRACT FROM AUTHOR]

XIDer is a 2D pixelated hybrid X-ray detector that is supposed to act as a multi-purpose platform for diffraction experiments at fourth-generation high-energy synchrotron light sources like the Extremely Brilliant Source of the European Synchrotron Radiation Facility (ESRF-EBS). As such it needs to tackle a wide variety of requirements. These include x-ray energies of 30 keV to 100 keV imposing the utilisation of high-Z sensors, a wide dynamic range from single photons to fluxes of 1 × 109 photons pixel−1 s−1 and expected raw data rates up to the order of TB s−1 in the final detector design. As a result, XIDer's readout ASIC has to provide smart and flexible ways for on-chip data pre-processing to reduce the output data rate to manageable sizes. This article focusses on introducing the ASIC's novel and unique data-handling concepts like the custom-designed telegram protocol followed by the presentation of exemplary configurations and use cases. [ABSTRACT FROM AUTHOR]

Abstract In this paper we present the Data Processor (DP) and the flight software of the EUSO-SPB1 mission. The EUSO-SPB1 experiment is a pathfinder mission of the EUSO program whose main objective is to detect Ultra-High Energy Cosmic Rays (UHECR) by measuring, for the first time from space, the fluorescence and the Cerenkov Ultra-Violet light produced by Extensive Air Shower. The instrument is a small telescope mounted on an unpressurized gondola of a super pressure balloon. Since a super pressure balloon could remain airborne up to 100 days, the requirements on the electronics and data handling are quite severe. The DP is the component of the electronics system performing the data handling, the monitoring, and the control of the instrument from ground through the interface with the telemetry system. EUSO-SPB1 was launched from Wanaka Airport (New Zealand) on the 24th of April 2017, at 22:51 UTC and the flight lasted for 12 days. [ABSTRACT FROM AUTHOR]

Abstract New physics experiments at the Facility for Antiproton and Ion Research (FAIR) in Darmstadt require application-optimized detector readout circuits. The STS/MUCH-XYTER2 (or SMX2) is a new, 128-channel prototype ASIC for silicon strip detectors and gas electron multiplier (GEM) detectors in the Compressed Baryonic Matter (CBM) experiment. It provides self-triggered amplitude and time measurement of incoming charge and serial streaming of digitized data. The 10 mm × 6.75 mm chip was fabricated employing the UMC CMOS 180 nm process. It comprises of an analog front-end with dual-path processing including a timing comparator in one path and a continuous-time 5-bit analog-to-digital converter in the other path, a digital back-end with time pre-sorting, advanced monitoring and throttling features and multiple 320 Mbps, serial links targeted for a GBT-based data acquisition structure. Specific conditions of the detector systems will be discussed prior to the structure and the features of the ASIC together with measurement results. [ABSTRACT FROM AUTHOR]

Vertex detectors provide space–time coordinates for the traversing charged particle decay products closest to the interaction point. Resolving these increasingly intense particle fluences at high luminosity particle colliders, such as SuperKEKB, is an ever growing challenge. This results in a non-negligible occupancy of the vertex detector using existing low material budget techniques. Consequently, new approaches are being studied that meet the vertexing requirements while lowering the occupancy. In this paper, we introduce a novel vertex detector architecture. Its design relies on an asynchronous digital pixel matrix in combination with a readout based on high precision time-of-flight measurement. Denoted the Timing Vertex Detector (TVD), it consists of a binary pixel array, a transmission line for signal collection, and a readout ASIC. The TVD aims to have a spatial resolution comparable to the existing Belle2 vertex detector. At the same time it offers a reduced occupancy by a factor of ten while decreasing the channel count by almost three orders of magnitude. Consequently, reducing the event size from about 1 MB/event to about 5.9 kB/event. [ABSTRACT FROM AUTHOR]

In this article, an encoder Application Specific Integrated Circuit (ASIC) for high-speed serial data transmission is presented. The ASIC implements a low-latency and low-overhead line code and is fabricated with a commercial 0.25-µm Silicon-on-Sapphire CMOS technology. The ASIC operates at 640 MHz with a latency of no greater than 6.25 ns and the overhead of 14.3%. The encoder will be integrated with a serialiser and will be used in the A Toroidal LHC ApparatuS Liquid Argon (LAr) calorimeter Phase-I trigger upgrade. [ABSTRACT FROM PUBLISHER]

We present the development of an automated testing system for the VMM hybrid of the RD51 collaboration. The VMM hybrid is a new front-end board for the RD51 common readout system, the Scalable Readout System, and will become the workhorse for the next decade to read out Micro-Pattern Gaseous Detectors. It uses the VMM chip developed for the ATLAS New Small Wheel to convert charge signals from detectors to digital data. Our testing system automatically characterises the quality of the VMM chips on the hybrid after production during multiple tests. Results are evaluated to classify the chips and hybrids and uploaded to a database. We evaluated those results for the first two production batches to measure the production yield. The yield is better than the threshold below which chip testing on a wafer level offers financial benefits. Observations on prominent chip failures were propagated back to the hybrid production process to further increase the yield for future productions. [ABSTRACT FROM AUTHOR]