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In this paper, the design and simulation results of a general-purpose fuzzy logic controller (FLC) with mixed-signal (analog and digital) inputs and digital outputs are presented. Based on a new strategy, it provides simplicity and high speed from the analog prospective and a total digital system advantages with unchanged digital system properties. A novel and reliable structure with respect to other topologies for the fuzzifier section is designed which enhances the accuracy and the velocity. In order to detect minimum and maximum of the input currents at the same time, an inference engine consisting of a min & max circuit is an addition. The benchmark for the defuzzifier in the proposed design is simplicity and through a simple approach, the center of area (COA) is attributed to the defuzzifier. The proposed controller circuit consists of two inputs, sixteen rules and one output designed in 0.35μm CMOS standard technology and simulated with MATLAB systematically. The total controller circuit is simulated with HSPICE simulator (BSIM3v3 parameters) and the layouts were extracted with Cadence Virtuoso v 5.1. The inference speed of the controller is about 41.3 MFLIPS (fuzzy logic inference per second) and power consumption is 3.2 mW. [ABSTRACT FROM AUTHOR]

One of the active areas of fuzzy logic applications is control systems. In this paper presents a proposed Fuzzy Logic Controller (FLC) chip utilized a novel Membership Function Circuit (MFC) which can be made programmable. This membership function features of large dynamic range, high current driving, high noise immunity and is simply tunable by setting some voltages on IC pins. Each input of controller has five membership functions and output has seven singletons. A new structure for Min/Max operators, and also, a new current-mode divider circuit with very small area, very low power consumption and high speed and accurate are presented, which are compatible to the proposed MFC, are also given. This controller is a general-purpose two-input one-output fuzzy controller that can be implemented in 0.08-mm2 in 0.35-μm CMOS technology (BSIM3v3). For general control tasks, input-output inference of FLC is voltage/voltage. The maximum delay in output of FLC is about 67-ns that correspond to 15-MFLIPS (Fuzzy Logic Inference per Second) and power consumption is 2.5-mW. [ABSTRACT FROM AUTHOR]

A novel high speed linear tunable transconductor suitable for analog and mixed-signal fuzzy circuits operating in current mode is proposed. Using this OTA, we construct a high speed fuzzifier and implement trapezoidal/triangular functions with all parameters (slope, width, and position) independently and continuously tunable, and excellent for low voltage applications. Computer simulations verify the performance of this circuit, showing high speed (up to 100 MHz) and a high support range (up to 2.5 V). [ABSTRACT FROM AUTHOR]

We propose an analog fuzzy logic controller chip structure in 1.2 μm CMOS technology. It employs a new architecture for fuzzifier circuit that generates membership functions with a very suitable range and precision. These membership functions are simply tunable by setting some voltages on IC pins. Input has three membership functions and output is five singleton membership functions. Also, a novel defuzzifier circuit is used which occupies a small chip area. The controller is tested for two inputs, one output, and nine tunable fuzzy rules. The proposed architecture has an operation speed of 6.25 MFLIPS (6.25×106 fuzzy logic inference per second) and power consumption of 16.3 mW. The whole chip area is less than 0.7 mm2 which is very small. Simulation tests show a good functionality of controller in response to some inputs to confirm the success of the design. The application of the system to the synthesis of a second-order system in a feedback loop is also considered. [Copyright &y& Elsevier]

In this paper, a membership function generator (MFG) is presented which can produce triangular, trapezoidal, S-shaped or Z-shaped membership functions. The presented structure can operate in both trans-conductance (voltage–current) and current mode (current–current) with high programmability. The slope (keeping the height or width of the membership function constant), height (keeping the width constant) and width (keeping the height constant) of the membership function are independently programmable. Moreover, the width of the trapezoid can be varied without changing slope or height and all the generated shapes can be positioned horizontally. The topology, primarily, is presented in transconductance mode which can be converted to current mode with a little change in the input section of the circuit. Simulation results for the proposed circuit are presented in two operation modes. The most remarkable feature of the proposed MFG is its capability of generating outputs while consumes a very low amount of power. The analytical analysis of the proposed circuits is also given in HSPICE using TSMC 0.18 μm CMOS technology. [ABSTRACT FROM AUTHOR]