Search

In this paper, the design and simulation results of a general-purpose fuzzy logic controller, 5-bit digital inputs, and analog output are presented. Based on a new strategy, it provides simplicity and high speed from the analog prospective and a total digital system advantages with unchanged digital system properties. A novel and reliable structure with respect to other topologies for the fuzzifier section is designed which enhances the accuracy and the velocity. In order to detect maximum, minimum, and mixed mode (both minimum and maximum) of the input voltages at the same time, an inference engine consisting of a min and max circuit is an addition. The benchmark for the defuzzifier in the proposed design is simplicity and through a simple approach, and the center of area is attributed to the defuzzifier. The proposed controller circuit consists of two inputs, nine rules and one output designed in TSMC standard 0.18 µm CMOS technology and simulated with MATLAB systematically. The total controller circuit is simulated with HSPICE simulator (BSIM3v3 parameters), and the layouts were extracted with Cadence Virtuoso v 5.1. The whole chip area is less than 0.7 mm2, inference speed of the controller is about 39.2 MFLIPS (fuzzy logic inference per second), and the average power consumption is 2.61 mW. [ABSTRACT FROM AUTHOR]

In this paper, the design and simulation results of a general-purpose fuzzy logic controller (FLC) with mixed-signal (analog and digital) inputs and digital outputs are presented. Based on a new strategy, it provides simplicity and high speed from the analog prospective and a total digital system advantages with unchanged digital system properties. A novel and reliable structure with respect to other topologies for the fuzzifier section is designed which enhances the accuracy and the velocity. In order to detect minimum and maximum of the input currents at the same time, an inference engine consisting of a min & max circuit is an addition. The benchmark for the defuzzifier in the proposed design is simplicity and through a simple approach, the center of area (COA) is attributed to the defuzzifier. The proposed controller circuit consists of two inputs, sixteen rules and one output designed in 0.35μm CMOS standard technology and simulated with MATLAB systematically. The total controller circuit is simulated with HSPICE simulator (BSIM3v3 parameters) and the layouts were extracted with Cadence Virtuoso v 5.1. The inference speed of the controller is about 41.3 MFLIPS (fuzzy logic inference per second) and power consumption is 3.2 mW. [ABSTRACT FROM AUTHOR]

Analog implementation of fuzzy logic controllers (FLCs) is the most efficient method when speed, power, and area are critical. Inference engine (IE) usually takes a large part of total die area when the FLC has a large number of rules. In this paper, a method is proposed to reduce size of the IE in analog implementations of FLCs. Since only a small number of rules may be fired simultaneously, thus a few inference blocks (IBs) may work at the same time in an IE. In the proposed method, reduction in size of the IE is achieved by sharing a few IBs between a large number of rules. To test the proposed method, a standard FLC is designed using both the regular method and the proposed method. By using the proposed method, total power consumption and active area are reduced by factors of 2.31 and 2.15, respectively. Moreover, inference speed is improved by a factor of 3.8 and output error is reduced by a factor of 2.5. All simulations have been performed in HSPICE using level 49 models for 0.35 um CMOS process with a 3.3V power supply. [ABSTRACT FROM AUTHOR]

One of the active areas of fuzzy logic applications is control systems. In this paper presents a proposed Fuzzy Logic Controller (FLC) chip utilized a novel Membership Function Circuit (MFC) which can be made programmable. This membership function features of large dynamic range, high current driving, high noise immunity and is simply tunable by setting some voltages on IC pins. Each input of controller has five membership functions and output has seven singletons. A new structure for Min/Max operators, and also, a new current-mode divider circuit with very small area, very low power consumption and high speed and accurate are presented, which are compatible to the proposed MFC, are also given. This controller is a general-purpose two-input one-output fuzzy controller that can be implemented in 0.08-mm2 in 0.35-μm CMOS technology (BSIM3v3). For general control tasks, input-output inference of FLC is voltage/voltage. The maximum delay in output of FLC is about 67-ns that correspond to 15-MFLIPS (Fuzzy Logic Inference per Second) and power consumption is 2.5-mW. [ABSTRACT FROM AUTHOR]

In this paper, an Anti-lock braking system (ABS) is designed using a fuzzy logic controller (FLC). The FLC is designed in 0.35 μm standard CMOS process and this design of the circuit makes it having high speed and low power consumption. Also, all the controlling signals and input signals are in voltage form and there is no need for digital programming. Voltage mode design of the circuits leads to the convenient use of FLC with sensors. The objective function is designed to keep the wheel slip to a desired level so that maximum wheel tractive force and maximum vehicle deceleration are achieved. By training this function to the Adaptive Nero-Fuzzy Inference System (ANFIS) of MATLAB software the main parameters of fuzzy controller singletons and shape of Membership Function Generators (MFGs) are measured, then all the circuits of the proposed fuzzy logic controller is designed using Complementary Metal-Oxide-Semiconductor (CMOS) circuits, at the end simulation results of the fuzzy logic controller using Hspice simulator and BSIM3v3 (Berkeley Short-Channel Insulated gate field effect transistor Model) parameters verifies the performance and functionality of the design. [ABSTRACT FROM AUTHOR]

We propose an analog fuzzy logic controller chip structure in 1.2 μm CMOS technology. It employs a new architecture for fuzzifier circuit that generates membership functions with a very suitable range and precision. These membership functions are simply tunable by setting some voltages on IC pins. Input has three membership functions and output is five singleton membership functions. Also, a novel defuzzifier circuit is used which occupies a small chip area. The controller is tested for two inputs, one output, and nine tunable fuzzy rules. The proposed architecture has an operation speed of 6.25 MFLIPS (6.25×106 fuzzy logic inference per second) and power consumption of 16.3 mW. The whole chip area is less than 0.7 mm2 which is very small. Simulation tests show a good functionality of controller in response to some inputs to confirm the success of the design. The application of the system to the synthesis of a second-order system in a feedback loop is also considered. [Copyright &y& Elsevier]