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A detailed study of gate length scalability and device performance of undoped-body with extremely thin silicon-on-insulator (ETSOI) MOSFETs with back gates is presented. The results demonstrated that the improvement of short channel characteristics leads to higher drive current [I.sub.DSAT] and lower extrinsic gate delay CV/I at a fixed OFF-state current [I.sub.OFF].

The length of thin oxide definition area (LOD) effects and the incorporation of the dummy poly gates on the performance of 45-nm P-MOSFETs with and without strained SiGe source/drain (S/D) are examined. The compressive stress from the SiGe S/D has dominated the LOD effect for dummy poly gate located outside the active area, whereas the LOD effect is controlled by the SiGe S/D stress within the dummy gate and the STI stress for dummy poly gate located within the active area.

An analytical surface potential model and 3-D ATLAS device simulations are used to investigate the impact of gate misalignment on the performance of dual-material double-gate (DMDG) silicon-on-insulator (SOI) n-MOSFET (metal-oxide-semiconductor field-effect transistor). Analytical and simulation results are consistent, which validates the proposed model for the DMDG SOI n-MOSFET.

The pulsed drain current-voltage ([I.sub.d]-[V.sub.g]) measurement technique with a range of pulse durations is used to investigate the intrinsic electron-trapping properties of high-[kappa] gate stacks and the impact of fast transient charging on the threshold voltage shift ([Delta][V.sub.t]) of MOSFETs. The ([Delta][V.sub.t]) values are observed to be strongly dependent on the high-[kappa] and interfacial layer thicknesses, with hafnium-based gate stacks exhibiting a similar trap density profile.

The development of a new physically based classical continuous potential distribution model based on the channel center for a short-channel effect undoped body symmetrical double-gate transistor is reported. The newly developed technique could be used to solve the two-dimensional Poisson's equation analytically in a rectangular coordinate system.

The general charge pumping model is used to determine impact of density, energy, and depth position for MOSFET with Si[O.sub.2] and high-K gate stacks. The results showed that at large biases, the energy region probed becomes fully depth dependent and is nearly the same regardless of the CP curve type.

The development of a new analytical electron low field mobility model using the shear-strain component and quantum confinement effect for use in drift-diffusion simulator is discussed. This model proves the advantage of (110) channel nMOSFETs with higher stress contact etch stop layer in reproducing the gate-bias dependence of (100) piezoresistance coefficients in bending experiments.

TCAD simulations of the hot-carrier-reliability assessment of the gate electrode workfunction engineered recessed channel (GEWE-RC) MOSFET is carried out. The simulation results showed a reduction in the hot-carrier-reliability metrics, which suggests the feasibility of the GEWE-RC MOSFET design for high-performance application in which hot-carrier reliability plays an important role.

The reduction in electron mobility in metal-oxide-semiconductor field-effect transistor (MOSFETs) with a TiN/Hf[O.sub.2]/Si[O.sub.2] gate stack is analyzed. The mobility reduction in MOSFETs integrating Hf[O.sub.2] layer is explained by remote charges located at Hf[O.sub.2]/Si[O.sub.2] interface.