7 results on '"Kulkarni, Abhijit"'
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2. Resolving Practical Design Issues in a Single-Phase Grid-Connected GaN-FET-Based Differential-Mode Inverter.
- Author
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Kulkarni, Abhijit, Gupta, Ankit, and Mazumder, Sudip K.
- Subjects
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FIELD-effect transistors , *MICROGRIDS , *GALLIUM nitride , *ELECTRIC inverters , *PHOTOVOLTAIC power systems , *POWER transformers , *VOLTAGE control - Abstract
Microinverters for grid-connected photovoltaic (PV) power conversion systems often require voltage boost due to the low dc voltage of the PV panels. A high-frequency (HF) transformer-isolated differential-mode Ćuk inverter (DMCI) is an attractive topology due to its inherent voltage boost capability and high power density. One of the significant operational issue of the DMCI addressed in this paper is the presence of lower order harmonic distortion in the injected grid current. It is shown that lower order odd and even harmonic voltages are generated with this topology. This problem is accentuated due to the low damping offered by the grid to harmonic voltages. A systematic low-complexity control design is proposed to address this issue. It is shown experimentally that the DMCI operates stably with effective attenuation of the lower order harmonics using the proposed design. Practical operational issues of the DMCI with fast switching GaN field-effect transistor (FET) devices are analyzed and solutions are proposed. It is shown that there can be significant HF noise generation in the DMCI with a frequency range higher than the switching frequency. Practical solutions for resolving HF issues using a combination of circuit layout design and additional passive components are proposed and validated. All of the experimental results are demonstrated on a 500-W GaN-FET-based microinverter prototype. [ABSTRACT FROM PUBLISHER]
- Published
- 2018
- Full Text
- View/download PDF
3. Design of a High-performance High-pass Generalized Integrator Based Single-phase PLL.
- Author
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Kulkarni, Abhijit and John, Vinod
- Subjects
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ELECTRIC current converter design & construction , *INTEGRATORS , *HIGH performance computing , *ELECTRIC power distribution grids , *PHASE-locked loops , *HARMONIC distortion (Physics) - Abstract
Grid-interactive power converters are normally synchronized with the grid using phase-locked loops (PLLs). The performance of the PLLs is affected by the non-ideal conditions in the sensed grid voltage such as harmonics, frequency deviations and the dc offsets in single-phase systems. In this paper, a single-phase PLL is presented to mitigate the effects of these non-idealities. This PLL is based on the popular second order generalized integrator (SOGI) structure. The SOGI structure is modified to eliminate the effects of input dc offsets. The resulting SOGI structure has a high-pass filtering property. Hence, this PLL is termed as a high-pass generalized integrator based PLL (HGI-PLL). It has fixed parameters which reduces the implementation complexity and aids in the implementation in low-end digital controllers. The HGI-PLL is shown to have the lowest resource utilization among the SOGI based PLLs with dc cancelling capability. Systematic design methods are evolved leading to a design that limits the unit vector THD to within 1% for given non-ideal input conditions in terms of frequency deviation and harmonic distortion. The proposed designs achieve the fastest transient response. The performance of this PLL has been verified experimentally. The results agree with the theoretical prediction. [ABSTRACT FROM AUTHOR]
- Published
- 2017
- Full Text
- View/download PDF
4. Design of a fast response time single-phase PLL with dc offset rejection capability.
- Author
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Kulkarni, Abhijit and John, Vinod
- Subjects
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PHASE-locked loops , *INTEGRATING circuits , *ELECTRIC inverters , *DIRECT currents , *HARMONIC distortion (Physics) - Abstract
Second-order generalized integrator (SOGI) based phase-locked loops (PLLs) are commonly used for grid voltage synchronization in single-phase grid-connected power converters. SOGI-PLLs are attractive because of their simple structure that makes them suitable for implementation even in low-end digital controllers. In this paper, an SOGI based fixed-parameter PLL structure with full dc offset rejection capability is presented. This PLL uses two cascaded SOGI structures and it is termed as cascaded generalized integrator PLL (CGI-PLL). A systematic design procedure is proposed for the CGI-PLL that minimizes the response time and unit vector harmonic distortion. This design achieves minimum settling time for any given worst-case frequency deviation in the grid voltage and ensures that the unit vector THD is less than 1%. The PLL designed using the proposed method has good harmonic attenuation capability. The steady-state and transient response of this PLL have been validated experimentally and are found to agree with the theoretical analysis. [ABSTRACT FROM AUTHOR]
- Published
- 2017
- Full Text
- View/download PDF
5. A novel design method for SOGI-PLL for minimum settling time and low unit vector distortion.
- Author
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Kulkarni, Abhijit and John, Vinod
- Abstract
Phase-locked loops (PLLs) are necessary in grid connected systems to obtain information about the frequency, amplitude and phase of the grid voltage. In stationary reference frame control, the unit vectors of PLLs are used for reference generation. It is important that the PLL performance is not affected significantly when grid voltage undergoes amplitude and frequency variations. In this paper, a novel design for the popular single-phase PLL topology, namely the second-order generalized integrator (SOGI) based PLL is proposed which achieves minimum settling time during grid voltage amplitude and frequency variations. The proposed design achieves a settling time of less than 27.7ms. This design also ensures that the unit vectors generated by this PLL have a steady state THD of less than 1% during frequency variations of the grid voltage. The design of the SOGI-PLL based on the theoretical analysis is validated by experimental results. [ABSTRACT FROM PUBLISHER]
- Published
- 2013
- Full Text
- View/download PDF
6. Analysis of Bandwidth–Unit-Vector-Distortion Tradeoff in PLL During Abnormal Grid Conditions.
- Author
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Kulkarni, Abhijit and John, Vinod
- Subjects
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PHASE-locked loops , *TELECOMMUNICATION , *CONVERTERS (Electronics) , *ELECTRIC distortion , *ELECTRIC potential - Abstract
Phase-locked loops (PLLs) are necessary in applications which require grid synchronization. Presence of unbalance or harmonics in the grid voltage creates errors in the estimated frequency and angle of a PLL. The error in estimated angle has the effect of distorting the unit vectors generated by the PLL. In this paper, analytical expressions are derived which determine the error in the phase angle estimated by a PLL when there is unbalance and harmonics in the grid voltage. By using the derived expressions, the total harmonic distortion (THD) and the fundamental phase error of the unit vectors can be determined for a given PLL topology and a given level of unbalance and distortion in the grid voltage. The accuracy of the results obtained from the analytical expressions is validated with the simulation and experimental results for synchronous reference frame PLL (SRF-PLL). Based on these expressions, a new tuning method for the SRF-PLL is proposed which quantifies the tradeoff between the unit vector THD and the bandwidth of the SRF-PLL. Using this method, the exact value of the bandwidth of the SRF-PLL can be obtained for a given worst case grid voltage unbalance and distortion to have an acceptable level of unit vector THD. The tuning method for SRF-PLL is also validated experimentally. [ABSTRACT FROM PUBLISHER]
- Published
- 2013
- Full Text
- View/download PDF
7. Mitigation of Lower Order Harmonics in a Grid-Connected Single-Phase PV Inverter.
- Author
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Kulkarni, Abhijit and John, Vinod
- Subjects
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HARMONIC series (Mathematics) , *ELECTRICAL harmonics , *ELECTRIC power distribution grids , *PHOTOVOLTAIC power systems , *ELECTRIC inverters , *ELECTRIC filters , *DYNAMICS - Abstract
In this paper, a simple single-phase grid-connected photovoltaic (PV) inverter topology consisting of a boost section, a low-voltage single-phase inverter with an inductive filter, and a step-up transformer interfacing the grid is considered. Ideally, this topology will not inject any lower order harmonics into the grid due to high-frequency pulse width modulation operation. However, the nonideal factors in the system such as core saturation-induced distorted magnetizing current of the transformer and the dead time of the inverter, etc., contribute to a significant amount of lower order harmonics in the grid current. A novel design of inverter current control that mitigates lower order harmonics is presented in this paper. An adaptive harmonic compensation technique and its design are proposed for the lower order harmonic compensation. In addition, a proportional-resonant-integral (PRI) controller and its design are also proposed. This controller eliminates the dc component in the control system, which introduces even harmonics in the grid current in the topology considered. The dynamics of the system due to the interaction between the PRI controller and the adaptive compensation scheme is also analyzed. The complete design has been validated with experimental results and good agreement with theoretical analysis of the overall system is observed. [ABSTRACT FROM AUTHOR]
- Published
- 2013
- Full Text
- View/download PDF
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