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Systematic characterizations of a cascode device with a low-voltage enhance-mode (E-mode) p-GaN gate high-electron mobility transistor as the control device and a high-voltage (HV) depletion-mode (D-mode) silicon carbide junction field effect transistor (JFET) as the voltage blocking device are presented in this article. The demonstrated device with a breakdown voltage rating of 1200 V and a static on-resistance (RON) of 100 mΩ features small device capacitances with fast switching speed, avalanche breakdown capability, thermally stable threshold voltage (VTH), and no dynamic RON degradation. To identify its safe operation in the off-state with a high drain bias, the off-state middle point voltage (VM) between the E-mode device drain and D-mode device source is investigated. A relatively low off-state VM is achieved under both static and dynamic modes. In addition to the device-level characterization, a custom-designed double-pulse test circuit is built to evaluate the transient switching performance of the cascode device. Optimal gate drive conditions are proposed to 1) overcome the drain bias induced positive dynamic VTH shift; and 2) suppress the increased dynamic off-state leakage current (IOFF) induced by on-state hole injection. Under 800 V/16 A testing conditions, high switching speed with the drain voltage peak slew rates of 72 V/ns during turn-on and 121 V/ns during turn-off is achieved. [ABSTRACT FROM AUTHOR]

In this paper, systematic characterization and the corresponding suppression strategies of dynamic OFF-state leakage current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) are presented based on fast pulsed ${I}$ – ${V}$ measurement and consecutive switching measurement. It is found that the high ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ under dynamic pulse mode without hole injection is a result of the reduced voltage blocking capabilities (both lateral and vertical) with weaker trapping effect in the buffer, and the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection is caused by further increased lateral conductivity through the buffer from source to drain. The corresponding behaviors under continuous waveforms with different switching conditions are analyzed to identify effective approaches for the suppression of dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ in practical switching operations. A higher temperature is shown to be beneficial to the reduction of the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection. To completely eliminate the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ caused by ON-state hole injection and minimize the OFF-state power consumption in practical power switching applications, a sufficiently large negative OFF-state gate bias (e.g., ${V}_{\text {GS}, \mathrm{\scriptscriptstyle OFF}}\le -{3}$ V) is recommended in the gate driver turn-off voltage design for the Schottky-type p-GaN gate HEMTs. [ABSTRACT FROM AUTHOR]

The OFF-state drain leakage characteristics in 600-V p-GaN HEMTs with an ohmic gate contact are investigated under dynamic switching conditions instead of commonly used quasi-static measurement setup. It is found that fast dynamic OFF-state leakage current (dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$) is substantially higher than the slow-ramping quasi-static ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ due to the weaker trapping effect in the buffer layer. With sufficiently large positive ON-state gate bias, further increase in dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ is observed and is attributed to ON-state hole injection that leads to energy band lowering in the buffer. The underlying physical processes are explained by the dynamic behavior of the traps in the buffer layer. This letter indicates that the ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ under practical switching operations is much higher than the static measurement results and should be used to evaluate dynamic OFF-state power consumption in the p-GaN HEMTs with an ohmic gate contact. [ABSTRACT FROM AUTHOR]

A previously reported normally-off GaN double-channel (DC-) MOS-HEMT with a gate recess into the upper channel layer has achieved a remarkably low R\text {on} . In this letter, we found that the double-channel structure itself does not guarantee a low R\text {on} without careful consideration of the electrical coupling between the two channels. A strong channel-to-channel (C2C) coupling between the two channels is critical to reduce R\text {on} in the DC-MOS-HEMT by exploiting both channels at the access region while allowing currents to converge into the heterojunction lower channel at the gate region. Otherwise, with a weak C2C coupling, the conduction through the upper channel is comprised due to the high-resistivity MOS-channel section at the gate region. The fabricated DC-MOS-HEMT with C2C distance ( t{\textsf {C2C}} ) of 7.5 nm exhibits an appreciably lower R\text {on} than that with t{\textsf {C2C}} = \textsf {11.5} nm. Further analysis reveals the latter suffers from an increased sheet resistance at access region compared with the sheet resistance of the DC-heterostructure itself. A modified TLM characterization is proposed to analyze the C2C coupling in the DC-heterostructure. It is confirmed the DC-heterostructure with t{\textsf {C2C}} = \textsf {7.5} nm boasts a strong C2C coupling, while that with t{\textsf {C2C}} = \textsf {11.5} nm features relatively weak C2C coupling. [ABSTRACT FROM PUBLISHER]

GaN-based digital integrated circuits (ICs) are realized on a 6-inch GaN-on-Si power high-electron-mobility transistor (HEMT) platform by monolithic integration of enhancement/depletion-mode HEMTs using a 0.5- \mu \textm gate technology. A direct-coupled FET logic inverter and a 101-stage ring oscillator are fabricated and characterized. The inverter exhibits a large input voltage swing, wide noise margin, and high temperature stability, while the ring oscillator features a small propagation delay of 0.1 ns/stage under a supply voltage of 4 V. These digital ICs can operate properly up to at least 200 °C and show great potential for GaN smart power IC applications. [ABSTRACT FROM PUBLISHER]