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In this study, the threshold voltage (VT) degradation mechanism for a hot electron stress (HES) under semi-ON state conditions in AlGaN/GaN high electron mobility transistors is analyzed. The drain current versus gate voltage (ID–VG) characteristic curves indicate that VT shifts in the positive direction after the stress. However, an abnormal phenomenon that VT continuously shifts in the positive direction even after recovery is observed. A result comparison of a negative bias stress (NBS) experiment indicates that a hole recombination in pre-existing buffer defects is crucial. Therefore, a complete model of VT degradation mechanism is proposed. Moreover, the proposed model is confirmed through an illumination experiment and a Silvaco simulation. [ABSTRACT FROM AUTHOR]

This study investigates the recovery behavior of GaN high-electron mobility transistors on SiC substrates under different hot-carrier stress conditions. The threshold voltage shifts positively due to hot electron trapping at the buffer layer under hot-carrier stress. However, the recovery between semi-on (Vt < VG < 0 V) hot-carrier stress and on-state (VG > 0 V) carrier stress is significantly different. This phenomenon is systematically discussed in terms of the applied gate voltage under stress condition, which affects the occupation of the surface donor states. After applying a semi-on hot-carrier stress, the threshold voltage continues to shift positively after relaxing the applied voltage. In contrast, the threshold voltage exponentially recovers after applying an on-state hot-carrier stress. Silvaco technology computer aided design (TCAD) simulation was performed to verify the effect of the surface donor state on the threshold voltages. Since switching between on-state and off-state in RF-applications includes both conditions, we suggest that the surface donor states are crucial to determine the failure of devices. [ABSTRACT FROM AUTHOR]

In this study, we fabricated an n- type fin field-effect transistor (FinFET) and a p- type FinFET (p-FinFET) to compare their hot carrier degradation (HCD) in 14-nm technology nodes. We analyzed the HCD under different gate voltages ($\text{V}_{\text {G}}$) and found that in a 14-nm technology node, the HCD of the p- FinFET was more serious than that of the n- type FinFET (n-FinFET). In addition, as $\text{V}_{\text {G}}$ increased, the HCD mechanism of the p- FinFET changed from electron–electron scattering (EES) to multiple-vibration excitation (MVE) faster than that of the n- FinFET did; thus, a larger threshold voltage ($\text{V}_{\text {T}}$) shift was observed for the n- FinFET. When $\text{V}_{\text {G}}$ increased to $\text{V}_{\text {T}}+1.2$ V for the n- FinFET and to $\text{V}_{\text {T}} -{0.8}$ V for the p- FinFET, $\Delta \text{V}_{\text {T}}$ began to increase rapidly under hot carrier stress. The distributions of $\tau \times {(}\frac {I_{B}}{I_{D}}{)}^{-{2.7}}$ - ${I}_{D}$ for the n- FinFET and p- FinFET used in this study indicated that the mechanism of HCD changed from EES to MVE as $\text{V}_{\text {G}}$ increased. This result suggests that the p- FinFET experienced more serious HCD than did the n- FinFET because of the dominance of MVE in the p- FinFET. The HCD mechanism changed with a lower $\text{V}_{\text {G}}$ value for the p- FinFET than for the n- FinFET. Finally, HCD occurred more uniformly in the entire channel for the p- FinFET than for the n- FinFET. [ABSTRACT FROM AUTHOR]

The generation of defect states in p-MOSFETs under negative bias temperature instability (NBTI) has been extensively discussed in previous literature. However, only a few studies have discussed the relationship between interface defects and off-state leakage. Therefore, this article analyzes the impact of interface defects generated by NBTI on gate-induced drain leakage (GIDL). In general, GIDL is generated through band-to-band tunneling (BTBT) at large gate-to-drain bias (VGD). In this article, NBTI causes an increase in GIDL at extremely low VGD. By measuring at different temperatures and comparing the GIDL generated from hot carrier degradation (HCD), it was confirmed that the GIDL would still be generated through trap-assisted tunneling (TAT) and thermal excitation at an extremely low VGD. [ABSTRACT FROM AUTHOR]

This letter investigates the mechanism of abnormal substrate current ($\text {I}_{\text {sub}}$) after hot carrier stress (HCS) in fin field effect transistors (FinFETs). Traditionally, after HCS, the drain current and $\text {I}_{\text {sub}}$ of the saturation region will continue to decrease. In this work, however, $\text {I}_{\text {sub}}$ first decreased and then exhibited a gradual abnormal rise. This abnormal $\text {I}_{\text {sub}}$ behavior was investigated by different measurement methods and was determined to be due to trap-assisted tunneling. This study first uses different operating voltages to prove the proposed model, then applies a variable temperature stress condition to confirm the model. Finally, a junction current measurement is used to determine the location of defect generation. [ABSTRACT FROM AUTHOR]

This work investigates the effects of HfO2 layer defects, formed by the Al atoms in the metal gate, on performance and reliability in advanced n-type metal–oxide–semiconductor field-effect transistors (n-MOSFETs) with different Al content in the gate stacks. Many groups have proposed theories (e.g., Si–H bond dissociation, trapped in high- ${k}$ defects and impact ionization) to explain the degradation mechanisms in MOSFETs, with most focusing on the dissociation of the Si-H bond at the Si/SiO2 interface and the carrier trapping in the high- $k$ layer. However, for multi- ${V}_{{\text {th}}}$ devices, experimental results indicate that the formation of defects by Al atoms in the HfO2 layer is the main reason for degradation in advanced n-MOSFETs. Therefore, we propose a mechanism to clarify the deterioration in advanced n-MOSFETs with different Al content in the gate stacks, and this mechanism is confirmed by positive bias temperature instability (PBTI), hot carrier instability (HCI), HCI power-law fitting and the gate-induced drain leakage (GIDL) measurement. [ABSTRACT FROM AUTHOR]

This letter discusses the hot carrier stress (HCS) degradation mechanisms for different gate voltages ($\text{V}_{\textsf {G}}$) in FinFET devices, and finds the abnormal relationship between HCS degradation and body current under high $\text{V}_{\textsf {G}}$. According to the distributions of lifetime (${\tau }$)- $\text{I}_{\textsf {B}}$ and ${\tau }$ -drain current ($\text{I}_{\textsf {D}}$), it is found that the ${\tau }$ under the high $\text{V}_{\textsf {G}}$ is related to the $\text{I}_{\textsf {D}}$ instead of the $\text{I}_{\textsf {B}}$. In addition, as the $\text{V}_{\textsf {G}}$ increases from low to middle to high values, the HCS degradation mechanism exhibits single vibrational excitation, electron-electron scattering, and multiple vibrational excitation (MVE) models, respectively. Therefore, the HCS degradation mechanism at higher $\text{V}_{\textsf {G}}$ is not dominated by the traditional impact ionization but by the carrier concentration of the channel. Finally, according to the results of fitting MVE model, the reason for breaking the Si-H bonds to form dangling bonds is the bending vibrational mode. [ABSTRACT FROM AUTHOR]