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A great current density–voltage ( J – V ) hysteresis with respect to the scan direction is important issue in perovskite hybrid solar cells because the power conversion efficiency is sometimes incorrect. Here, we demonstrated >17% mesoscopic CH 3 NH 3 PbI 3 (MAPbI 3 ) perovskite hybride solar cells without significant J – V hysteresis with respective to the scan direction and rated by using Li-treated mesoscopic TiO 2 electrode. The Li-treated mesoscopic TiO 2 electrode improved charge separation/injection from MAPbI 3 into mesoscopic TiO 2 , charge transport in mesoscopic TiO 2 , and surface traps because the conduction band edge of mesoscopic TiO 2 was lowered by ~0.1 eV, the mobility of charge carriers was increased from ~1.1×10 −6 cm 2 /V s to ~2.5×10 −6 cm 2 /V s, the conductivity of mesoscopic TiO 2 was increased from ~5.6×10 −7 S/cm to ~1.6×10 −6 S/cm, and the trap density was reduced from ~1.2×10 16 cm −3 to ~9.3×10 15 cm −3 through Li-treatment. Therefore, the average power conversion efficiency was significantly enhanced from 14.84% to 17.26% at 1 sun condition by the Li-treatment of mesoscopic TiO 2 .

The dependence of hysteresis characteristics in low temperature poly‐Si (LTPS) thin film transistors (TFTs) on the gatesource voltage (Vgs) or the drain‐source voltage (Vds) bias is investigated and discussed. The hysteresis levels in both p‐type and n‐type LTPS TFTs are independent of Vds bias but increase as the sweep range of Vgs increases. It has been found that the hysteresis in both p‐type and n‐type LTPS TFTs originated from charge trapping and de‐trapping in the channel region rather than at the source/drain edges.

A vertical-gate Si/SiGe double heterojunction bipolar transistor (VerDHBT)-based capacitorless 1T DRAM cell is proposed for improved storage performance with a fabrication feasibility through a selective epitaxy. It is verified through a TCAD device simulation for dc and transient characteristics of the proposed VerDHBT-based 1T DRAM. The off-state leakage current was significantly reduced, while the on-current was considerably increased with SIF/Bmid/DIF = SiGe/SiGe/Si as the interfacial source/middle body/interfacial drain. A large hysteresis window for the “read 1” from the “read 0” and a long retention time at low latch voltage could be also obtained.

Although the record efficiencies of perovskite hybrid solar cells are gradually reaching the efficiency of crystalline Si solar cells, perovskite hybrid solar cells often exhibit significant current density–voltage (J–V) hysteresis with respect to the forward and reverse scan direction and scan rate. The origin of the J–V hysteresis of perovskite hybrid solar cells has not, to date, been clearly elucidated. Dielectric polarization by the ferroelectric properties of perovskite (i), the ionic motion/migration of perovskite materials (ii), and charge trapping and detrapping at trap sites by the unbalanced electron and hole flux (iii) are considered the possible origins of J–V hysteresis. Here, we reviewed the origin of the J–V hysteresis of perovskite solar cells from the above three points of view and we then suggest how one may reduce the J–V hysteresis with respect to the scan direction and scan rate.

A silicon nanowire field effect transistor (SiNW FET) was fabricated through the fabrication method compatible with that of MOSFET including back-end process without lift-off process. However, when it is working in an aqueous solution, the SiNW device as well as other transducer devices has various inherent instability problems such as hysteresis characteristics. We observed the hysteresis in DI water (DW) and confirmed that it is caused by mobile ion effect in DW with various experimental results.

Bilayer type CH3NH3PbI3 (MAPbI3) perovskite hybrid solar cells were fabricated via a one-step spin-coating process by using solubility controlled MAPbI3 solutions of MAPbI3-DMSO (dimethyl sulfoxide) and MAPbI3-DMF (N, N-dimethylformamide)-HI. The best DMSO-bilayer device showed 1.07 ± 0.02 V V(oc) (open-circuit voltage), 20.2 ± 0.1 mA cm(-2) J(sc) (short-circuit current density), 68 ± 2% FF (fill factor), and 15.2 ± 0.3% η (overall power conversion efficiency) under the forward scan direction and 1.07 ± 0.02 V V(oc), 20.4 ± 0.1 mA cm(-2) J(sc), 70 ± 3% FF, and 15.9 ± 0.4% η under the reverse scan direction. The best HI-bilayer device had 1.08 ± 0.02 V V(oc), 20.6 ± 0.1 mA cm(-2) J(sc), 75 ± 1% FF, and 17.2 ± 0.2% η under the forward scan direction and 1.08 ± 0.02 V V(oc), 20.6 ± 0.1 mA cm(-2) J(sc), 76 ± 2% FF, and 17.4 ± 0.3% η under the reverse scan direction. The deviation of average device efficiency (η(avg)) of 20 DMSO samples and 20 HI samples was 14.2 ± 0.95% and 16.2 ± 0.85%, respectively. Therefore, the HI-bilayer devices exhibited better device efficiency and smaller J-V (current density-voltage) hysteresis with respect to the scan direction than the DMSO-bilayer devices due to the reduced recombination and traps by the formation of a purer and larger MAPbI3 perovskite crystalline film.

The silicon nanowire (SiNW) biosensors, one of the most promising candidates of the electrical biosensor transducer, show various peculiar electrical phenomena under the electrolyte environment, including hysteresis occurring in the I–V measurement, which make it difficult to develop reliable biosensor systems. In this paper, we build up an electrical model of the biosensor system comprised of the electrolyte liquid, SiNW and the back-gate substrate. We show that the current hysteresis is caused by the change of liquid charges though the suggested unified electrical model of the electrolyte-SiNW system and presented various experimental results.

The hysteresis phenomenon has been widely observed in transfer characteristics of silicon nanowire (SiNW) biosensor devices in aqueous environment. Considering the experimental observation in the change of the liquid potential due to the charge flow through the oxide layer, we build up an electrical model for the biosensor system with the solution, SiNW, dielectric oxide, and the back-gated substrate, and investigate the hysteresis behavior based on the model.

Bias temperature-dependent characteristics of nanoscale silicon-oxide-nitride-oxide-silicon memories are investigated under program/erase (P/E) Fowler–Nordheim (FN) stresses. In the erased cell, FN stress time evolution is found to be a similar physical process to the recovery of interface traps (NIT) that takes place under the dynamic negative bias temperature instability stress. In addition, anode hole injection induced holes are trapped in the bottom oxide, both in the erase and in the read conditions of the erased cell, and make significant roles in the reverse hysteresis and higher power-law exponent n at higher temperature in P/E cycled erased cells. While the temperature-independent n=0.3 is observed in the programed cell, the temperature-sensitive n=0.36–0.66 is observed in the erased cell.