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To achieve a highly reliable IGZO transistor, silicon nitride thin film, as a passivation layer, has been extensively investigated in recent years, mainly due to readily available fabrication, along with good barrier performance. Here, we found out that larger amount hydrogen residuals was observed in the PECVD deposited SiNx passivation layer, more stable the IGZO oxide device exhibited, which is abnormal behavior to that commonly known in the literatures. Given that FT‐IR and SIMS analysis with various controlled SiNx thin film upon different deposition conditions, the plasma parameters such as power, pressure, source gas ratio could affect hydrogen ion diffusivity into the IGZO layer during the deposition and the chemical composition of hydrogen residuals in the resulting SiNx layer, which is more dominant, rather than absolute hydrogen contents itself, to the initial electrical properties as well the stability of the IGZO transistor device. [ABSTRACT FROM AUTHOR]

Recently, digital X‐ray detector (DXD) technology is needed to implement high‐resolution and high‐definition images, and low‐dose exposure of X‐ray imaging systems. This technology requires the IGZO TFT structure with better mobility and lower leakage current than the a‐Si backplane. In order to supplement stability and improve PIN diode (photodiode) performance, when SiNx‐based insulating layers and thick photodiodes are applied, continuous damage due to high concentration impurities occurs in the plasma environment, and thus the threshold voltage (Vth) shift problem of the IGZO TFT transistor occurs. To solve this problem, a high performance partial passivation‐less structure (PPLS) was applied to prevent damage using 43×43 centimeter flat panel X‐ray detector, and we investigated the improvement of the IGZO TFT characteristics. Before PIN diode deposition, Vth was +0.24V and after PIN diode & SiNx deposition, it moved slightly to Vth ‐0.17V, but the same characteristics as initial performance were guaranteed after TFT was completed. [ABSTRACT FROM AUTHOR]

Recently, the digital X‐ray detector (DXD) technology requires high quality and high frame rate dynamic images, so efforts are being made to apply an oxide semiconductor (OS) thin film transistor (TFT) to the DXD backplane as a switching device instead of an amorphous Si (a‐Si) TFT. In order for the OS TFT to be used as a switching device of the X‐ray detector, it is necessary to study about the degradation parameters of the OS TFT under X‐ray irradiation. We confirmed that the threshold voltage (Vth) of the InGaZnO (IGZO) TFTs shifted negatively without s‐factor degradation according to X‐ray exposure. To understand these characteristics, we evaluated the X‐ray degradation characteristics of various methods. [ABSTRACT FROM AUTHOR]

An excess oxygen‐peroxide‐based model that can simultaneously analyze the positive‐bias‐stress (PBS) and negative‐bias‐illumination‐stress (NBIS) instabilities in commercial self‐aligned top‐gate (SA‐TG) coplanar indium–gallium–zinc oxide (IGZO) thin‐film transistors (TFTs) is proposed herein. Existing studies have reported that the transition of oxygen vacancy (VO) charge states from VO0 to VO2+ is the dominant physical mechanism responsible for the negative shift of threshold voltage (VTH) under NBIS. However, in this study, it is observed that both the PBS and the NBIS stabilities of IGZO TFTs deteriorate at a faster rate as the amount of oxygen increases within the channel layer, implying that the conventional VO‐related defect model is inappropriate in elucidating the PBS and NBIS instabilities of commercial SA‐TG coplanar IGZO TFTs, where the channel layers are formed under high oxygen flow rates (OFRs) to make VTH positive. On the basis of the full‐energy range subgap density of states extracted before and after each stress from IGZO TFTs with different OFRs, it is determined that the generation and annihilation of the subgap states in the excess oxygen peroxide configuration are the dominant physical mechanisms for PBS and NBIS instabilities in commercial SA‐TG coplanar IGZO TFTs, respectively. [ABSTRACT FROM AUTHOR]

Density effects of IGZO films were studied based on DFT calculations, and the electrical and physical properties between the high‐density film and the conventional film were compared. As the density increased, the carrier concentration, hole mobility, and the optical energy band gap of the IGZO film increased. Additionally, micro‐pore defects were not observed in the high‐density film unlike the conventional film through HR‐TEM cross‐sectional analysis. Also, we fabricated coplanar TFT devices with different density IGZO films and conducted PBTS and NBTiS reliability tests. The device with high‐density IGZO film was showed superior reliability characteristics [ABSTRACT FROM AUTHOR]

In order to obtain a robust gate dielectric, the nitrogen atom incorporation in the silicon oxide thin film has been investigated in much prior study in recent years. Silicon oxide thin film deposition is mainly performed using SiH4‐N2O plasma by the Plasma enhanced chemical vapor deposition (PECVD) system. Reducing the N2O/SiH4 gas flow ratio increases the nitrogen content in the film. However, the film uniformity dramatically deteriorates as the N2O/SiH4 ratio is decreased and this issue makes the low N2O/SiH4 ratio condition a challenging area for the process condition. In this study, to overcome this problem Argon (Ar) addition was employed to the low N2O/SiH4 ratio plasma and we found that Ar not only allows the thin film to be uniformly deposited by increasing the plasma density due to the penning effect, but also increases Si‐N bond especially under the ratio of 10:1 condition. Even though the silicon oxide thin film was deposited with low N2O/SiH4 gas flow rate, the film uniformity and breakdown voltage characteristics dramatically improved by Ar dilution. In addition, LTPS p‐channel TFT was fabricated by utilizing the improved silicon oxide thin film as a gate dielectric layer and it showed excellent electrical characteristics. This work would be one of the most practical solutions for robust gate dielectric deposition. [ABSTRACT FROM AUTHOR]

Stretchable electronic devices should be enabled by the smart design of materials and architectures because their commercialization is limited by the tradeoff between stretchability and electrical performance limits. In this study, thin‐film transistors are fabricated using strategies that combine the unit process of a novel hybrid gate insulator and low‐temperature indium gallium tin oxide (IGTO) channel layer and a stress‐relief substrate structure. Novel hybrid dielectric films are synthesized and their molecular structural configurations are analyzed. These films consist of a polymer [poly(4‐vinylphenol‐co‐methylmethacrylate)], cross‐linkers having different binding structures [1,6‐bis(trimethoxysilyl)hexane (BTMSH), dodecyltrimethoxysilane, and poly(melamine‐co‐formaldehyde)], and an inorganic zirconia component (ZrOx). The hybrid film with BTMSH cross‐linker and 0.2 M ZrOx exhibits excellent insulating properties as well as mechanical stretchability. IGTO transistors fabricated on polyimide‐coated glass substrates are transferred to the rubber substrate to offer stretchability of the transistor pixelated thin‐film transistors. IGTO transistors fabricated on stretchable substrates using these strategies show promising electrical performance and mechanical durability. After 200 stretchability test cycles under uniaxial elongation of approximately 300%, the IGTO transistor still retains a high carrier mobility of 21.7 cm2 V−1 s−1, a low sub‐threshold gate swing of 0.68 V decade−1 and a high ION/OFF ratio of 2.0 × 107. [ABSTRACT FROM AUTHOR]

This paper reports the effect of the cation composition on the electrical properties of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) where atomic layer deposition (ALD) was used to deposit an a-IGZO channel layer. The In0.38Ga0.18Zn0.44O transistors at a 200°C annealing temperature exhibited 39.4 cm2/V·s field effect mobility (µFE), −0.12 V threshold voltage (VTH), 0.40 V/decade subthreshold gate swing (SS), and >107 ION/OFF ratio, corresponding to the state-of-the-art characteristics of transistors with a sputtered IGZO channel. Further enhancement of the μFE value was observed for the devices with a higher In fraction: the In0.45Ga0.15Zn0.40O transistor had a higher μFE value of 48.3 cm2/V·s, −4.06 V VTH, 0.45 V/decade SS, and >107 ION/OFF ratio. The cation composition dependence on the performance of the a-IGZO TFTs was explained by analysing the density-of-state (DOS) distribution for the corresponding devices using the experimental independent variable (IV) and theoretical Technology Computer-aided Design (TCAD) simulation. [ABSTRACT FROM AUTHOR]

We report the effect of the cation composition on the electrical performance of amorphous indium gallium zinc oxide (a‐IGZO) thin‐film transistors (TFTs) which was deposited by atomic layer deposition (ALD). The In/In+Ga ratio of a‐IGZO TFT was increased, enhancement of the field‐effect mobility (µFE) value was observed. The device with a higher In/In+Ga ratio: the In0.45Ga0.15Zn0.40O transistor showed a higher µFE value of 48.3 cm2/Vs, VTH of −4.06 V, SS of 0.45 V/decade, and ION/OFF ratio of > 107. Simultaneously, Density of States (DOSs) profile in a forbidden band gap of the a‐IGZO semiconductor were extracted based on the Meyer‐Neldel rule (MN rule) to obtain an insight into the cation composition dependent performance of a‐IGZO TFTs. [ABSTRACT FROM AUTHOR]

The structural, chemical, and electrical properties of amorphous indium gallium zinc oxide (a-IGZO) films by magnetron sputtering and atomic layer deposition (ALD) were investigated where both a-IGZO films had a comparable cation composition. The ALD-derived a-IGZO film exhibited the higher atomic packing density, the effective suppression of trap-like oxygen vacancy defect (VO), and the enhancement in the hybridization of the sp orbital of In, Ga, and Zn cations compared to those of the sputtered a-IGZO film. Hence, a significant improvement in terms of the field-effect mobility was observed for the thin-film transistors with an In0.50Ga0.34Zn0.16O channel by ALD (36.6 cm $^{\textsf {2}}/\text{V}\cdot \text{s}$) compared to that of the sputtered In0.48Ga0.38Zn0.14O transistor (20.1 cm $^{\textsf {2}}/\text{V}\cdot \text{s}$); the ${I}_{\text {ON/OFF}}$ ratios for both were ~107. Simultaneously, the gate bias stress stability and photobias stress stability were also improved for the IGZO transistors with an ALD-derived channel, which can be explained by its reduced trap-like VO density. [ABSTRACT FROM AUTHOR]

The electrical properties and the device reliability under positive/negative bias stress with/without illumination regarding amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) are evaluated as a function of the nitrogen partial pressure in the sputter deposition. Interestingly, it is easy to control the carrier concentration through the incorporation of nitrogen into IGZO, whereby the device performance is changed. In addition, when nitrogen is introduced during the conventional IGZO deposition, the device reliability of N-doped IGZO TFTs is considerably improved compared to that of undoped-IGZO TFTs due to the reduced amount of defects. It is also interesting that such an improvement of the device reliability regarding IGZO is easily obtainable through the simple addition of nitrogen to the conventional deposition process. It is, therefore, strongly believed that this simple nitrogen-doping process for IGZO is very effective regarding the achievement of highly durable devices, and it can be immediately applied to the current mass production of the high-performance displays for which the oxide semiconductor is used. [ABSTRACT FROM AUTHOR]

This letter reports the fabrication of high-performance amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) via atomic layer deposition at a substrate temperature of 250 °C. The film thickness of In2O3, Ga2O3, and ZnO varied linearly with the number of deposition cycles. The cation composition of the IGZO film was controlled by an alternate stacking of In2O3, Ga2O3, and ZnO atomic layers. The fabricated a-IGZO TFTs exhibited a high electron mobility of 22.1 cm2/Vs, threshold voltage of 2.41 V, subthreshold gate swing of 0.30 V/decade, and an ${I}_{{ \mathrm{\scriptscriptstyle ON}}/{ \mathrm{\scriptscriptstyle OFF}}}$ ratio of $> \textsf {1} \times \textsf {10}^{\textsf {8}}$. [ABSTRACT FROM AUTHOR]

We propose an experimental method to decompose the positive gate-bias stress (PBS)-induced threshold voltage shift ( \Delta V\mathsf {th}) of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) into the contributions of distinct degradation mechanisms. Top-gate self-aligned coplanar structure TFTs are used for this letter. Stress-time-divided measurements, which combine the subgap density-of-states (DOS) extraction and the analysis on recovery characteristics, are performed to separate the \Delta V\mathsf {th} components. Change in excess oxygen ( \textO\mathsf {ex}) -related DOS is clearly observed, and \Delta V\mathsf {th} by PBS is quantitatively decomposed into the contributions of the active \textO\mathsf {ex} , and the deep and shallow gate insulator traps. The quantitative decomposition of PBS-induced \Delta V\mathsf {th} provides physical insight and key guidelines for PBS stability optimization of a-IGZO TFTs. [ABSTRACT FROM AUTHOR]

Decomposition of the positive gate-bias temperature stress (PBTS)-induced instability into contributions of distinct mechanisms is experimentally demonstrated in top-gate self-aligned coplanar amorphous InGaZnO thin-film transistors and validated by reproducing the PBTS time-evolution of I-V characteristics through the TCAD simulation into which the extracted density-of-states and charge trapping are incorporated. [ABSTRACT FROM AUTHOR]

Analysis on the light influx into a bottom-gate, etch-stopper structure thin-film transistor is presented. Reduction of the light influx by means of structural changes in the device can lead to a universal improvement in negative-bias temperature illumination stress instability of metal–oxide transistors. When the devices are illuminated by a fixed light source from below, the dominant light influx occurs in the channel-width direction, due to light reflections off the boundary between the passivation layer and the ambient. Wave propagation into the channel can be suppressed by using thinner dielectric layers or applying an overlying coating layer with a larger refractive index than that of the passivation dielectric material. [ABSTRACT FROM PUBLISHER]

We investigated the PBTS instability of top‐gate self‐aligned coplanar a‐IGZO TFTs with multilayer SiO2 GI. It is confirmed that the PBTS instability due to the deep charge trapping in GI bulk can be improved by increasing activation energy through the interfacial formation with hydrogen‐low SiO2 deposition, and it is demonstrated experimentally that the PBTS instability due to the excess oxygen in the active region can be improved by hydrogen diffusion process through sequential hydrogen‐rich SiO2 deposition after ACT/GI interface formation. [ABSTRACT FROM AUTHOR]

We investigate the effect of crystalline indium–gallium–zinc-oxide (c-IGZO) thin films on device performance, and evaluate the device reliability of c-IGZO under positive/negative bias stress with/without illumination. The crystal structure of deposited-IGZO thin film is controlled by annealing temperatures, and the transition from an amorphous to a crystalline structure is observed at above 800 °C. Even though the c-IGZO thin-film transistors (TFTs) exhibit lower carrier mobility, compared with amorphous IGZO (a-IGZO) TFTs, the remarkable improvement of the device reliability for the c-IGZO TFTs is observed especially under the bias stress with illumination. This comes from lower defect density compared with the a-IGZO film. [ABSTRACT FROM AUTHOR]

We demonstrate top-gate and bottom-gate structures of amorphous indium–gallium–zinc-oxide thin-film transistors and compare their device operation. A replica material stack is fabricated for depth profile characterization to correlate with device results. We mainly focus on the oxygen content at the top and bottom. Key process factors that affect device reliability are determined based on material analysis, subgap density-of-states extraction by monochromatic photonic capacitance-voltage technique, and device simulations. We found that top-gate devices are influenced by higher deep acceptor-like states under positive gate bias-temperature stress, whereas the bottom-gate devices suffer reliability degradation under negative gate bias-temperature stress due to the decrease in oxygen content at the bottom interface. [ABSTRACT FROM AUTHOR]

We report temperature sensors with amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs). The threshold voltage of a-IGZO TFTs shows linear dependency with temperature, which enables them to be used for temperature sensing. The single TFT sensor is simple, but its sensitivity is not high. However, significantly better sensitivity can be achieved by connecting several TFTs in a parallel series to create a multi-TFT sensor. The performances of the TFT sensors fabricated both for single and multi-TFTs are well matched with simulation results. [ABSTRACT FROM PUBLISHER]

A highly flexible amorphous indium–gallium–zinc–oxide (a-IGZO) thin film transistor (TFT) was tested with respect to the in-plane axis location and device architecture in a bending system. Short channel a-IGZO TFTs were fabricated based on the conventional coplanar configuration and the islanded structure on a polyimide (PI) substrate and were then subjected to a cyclic bending of 1 × 10 5 with varying radii smaller than a few mm. Embedding the devices at a neutral position in bending system allowed them to function well when exposed to the induced mechanical strain, regardless of the difference in the structural geometry. However, placement of the TFTs outside of the neutral surface resulted in a drastic suppression of the strain-induced electrical failure for the island configuration as the distance of the TFTs from the neutral surface increased. By contrast, the conventional structure, when placed outside the neutral surface, showed strongly accelerated device failure as the strain on the TFTs was increased. The electromechanical integrity was maintained for island-structured TFTs under a bending stress with a radius of 1 mm and a position margin of 50 μm away from the neutral surface. The brittle and rigid characteristics of TFT arrays with inorganic components are still considered problematic in terms of being put into practical use in flexible applications; nevertheless, the high flexibility achieved by this structural design and its geometrical characterization along the in-plane axis shows the great potential for a-IGZO TFTs to serve as the functional building blocks of new platform applications, such as rolling or folding displays, by suppressing the mechanical strain in the backplane. [ABSTRACT FROM AUTHOR]