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A wireless 3D NoC architecture is described for building-block SiPs, in which the number of hardware components (or chips) in a package can be changed after chips have been fabricated. The architecture uses inductive-coupling links that can connect more than two examined dies without wire connections. Each chip has data transceivers for the uplink and downlink in order to communicate with its neighboring chips in the package. These chips form a vertical unidirectional ring network so as to fully exploit the flexibility of the wireless approach that enables us to add, remove, and swap the chips in the ring. To avoid protocol and structural deadlocks in the ring, we use bubble flow control, which does not rely on the conventional VC-based deadlock avoidance mechanism. In addition, we propose a bidirectional communication scheme to form a bidirectional ring network by using the inductive-coupling transceivers that can dynamically change the communication modes, such as TX, RX, and Idle modes. This paper illustrates the inductive-coupling transceiver circuits, which can carry high data transfer rates of up to 8 Gbps per channel, for the wireless 3D NoC. It also illustrates an implementation of a wireless 3D NoC that has on-chip routers and transceivers implemented with a 65 nm process in order to show the feasibility of our proposal. The vertical bubble flow control and conventional VC-based approach on the uni- and bidirectional ring networks are compared with the vertical broadcast bus in terms of throughput, hardware amount, and application performance using a full system multiprocessor simulator. The results show that the proposed bidirectional communication scheme efficiently improves application performance without adding any inductive-coupling transceivers. In addition, the proposed vertical bubble flow network outperforms the conventional VC-based approach by 7.9-12.5 percent with a 33.5 percent smaller router area for building-block SiPs connecting up to eight chips. [ABSTRACT FROM PUBLISHER]

This paper presents a 30 Gb/s/link 2.2 Tb/s/mm^2 inductive-coupling link for a high-speed DRAM interface. The data rate per layout area is the highest among DRAM interfaces reported up to now. The proposed interface employs a high-speed injection-locking CDR technique that utilizes the derivative property of inductive coupling. Compared to conventional injection-locking CDR based on an XOR edge detector, the proposed technique doubles the operation speed and increases the data rate to 30 Gb/s/link. As a result, the data rate per layout area is increased to 2.2 Tb/s/mm^2, which is 2X that of the state-of-the-art inductive-coupling link, and 22X that of the state-of-the-art wired link. [ABSTRACT FROM PUBLISHER]

This paper presents a 10 fJ/bit inductive-coupling data link operating at 0.55 V supply voltage and a 135 fJ/cycle clock link at 0.7 V supply voltage. A dual-coil transmission scheme reduces the number of stacked transistors in a transmitter, enabling low-voltage and hence low-power operation. A test chip is fabricated in 65 nm CMOS whose nominal supply voltage is 1.2~V. A data rate of 1.1 Gb/s and a clock rate of 3.3 GHz, both with an error rate <10^-12, are achieved at 0.55 V and 0.7 V supply voltage, respectively. [ABSTRACT FROM AUTHOR]

A small-size inductive-coupling dc voltage transceiver for highly-parallel wafer-level testing is experimentally demonstrated in 90-nm CMOS technology, which can reduce the total cost of a low-price IC by 18%. In order to carry out dc tests, the proposed transceiver outputs dc voltage to the die-under-test (DUT) without any area-consuming digital circuits. In addition, digital calibration with digital feedback channel which calibrates the output dc voltage enables the removal of calibration circuits on the DUT. All of the circuits for dc tests are implemented into the area of an inductor (100 \mu\ m \times \,100 \mu\ m). The proposed dc voltage transmission is successfully demonstrated with 6-bit resolution. [ABSTRACT FROM PUBLISHER]

This paper describes a three-dimensional (3-D) system integration of a full-fledged processor chip and two memory chips using inductive coupling. To attain a 3-D communication link with a smaller area and lower power-consumption, shortening the link distance and preventing signal degradation due to unused inductors are important challenges. Therefore, we developed a new 3D-integrated wire-penetrated multi-layer structure for a shorter link distance and an open-skipped-inductor scheme for suppressing signal degradation. In addition, to avoid undefined-value propagation in stacking multi-memories using an inductive-coupling link, we proposed a memory-access-control scheme with a pinpoint-data-capture scheme. We demonstrate that three fabricated chips can be successfully AC-coupled using inductive coupling. The power and area efficiency of the link are 1 pJ/b and 0.15 mm²/Gbps, respectively, which are the same as those of two-chip integration. [ABSTRACT FROM AUTHOR]

An inductive-coupling programmable bus for NAND flash memory access in Solid State Drive (SSD) is presented. Compared to the conventional SSD, this wireless interface using relayed transmission reduces power consumption to 1/2, I/O circuit-layout area to 1/40, and achieves a data rate of 2 Gb/s in 0.18 μm CMOS process. In addition, since this wireless interface enables one package to contain 64 chips, the number of packages is reduced to 1/8. [ABSTRACT FROM AUTHOR]

A high-speed inductive-coupling link is presented. It communicates at a data rate of 11 Gb/s for a communication distance of 15 μm in 180 nm CMOS. The data rate is II x higher than previous inductive-coupling links. The communication distance is 5 x longer than a capacitive-coupling link for the same data rate, bit error rate, and layout area. Burst transmission utilizing the high-speed inductive-coupling link is also presented. Multi-bit data links are multiplexed into a single burst data link. It reduces layout area by a factor of three in 180 nm CMOS and a factor of nine in 90 nm CMOS. [ABSTRACT FROM AUTHOR]

A transceiver for inductive-coupling is realized. By using a pulse-shaping circuit, the transmitter energy is 0.11 pJ/b. Due to device scaling from 180 nm CMOS to 90 nm CMOS, the receiver energy is 0.03 pJ/b. The overall energy dissipation is 20X lower than previous work, without degrading the data rate of 1 Gb/s. [ABSTRACT FROM AUTHOR]