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Multilevel converters have many power devices and drivers. Thus, a direct reliability calculation based only on the first failure occurrence on one of the components clearly leads them to be devalued compared to two-level converters. However, taking into account that symmetrical multilevel converters such as the X-level active neutral point clamped (ANPC) family are based on imbricated and/or stacked switching cells on the one hand, with an additional center tap at the dc bus in three-phase operation on the other hand, several redundancies clearly appear which can be managed to increase the global reliability. For the first time, a general and theoretical methodology used to calculate reliability laws and failure rates and applied to compare two-, three-, and five-level topologies is proposed. Results show that the fault handling of three- and five-level three-phase topologies permits a great increase in reliability over a “relatively” short time duration, in addition to other benefits. [ABSTRACT FROM PUBLISHER]

This article deals with the monolithic integration in silicon of a multiphase static power converter (dc/ac or ac/dc) for medium power applications, from few kilowatts to few tens of kilowatts with power devices’ blocking capability in the range of 600–1200 V. This article presents an original three-chip integration approach that combines both monolithic integration in silicon and printed circuit board (PCB) packaging process and takes advantage of both silicon-level technology and PCB-level technology within a limited and well-mastered complexity. The converter is integrated within only three new multiterminal power chips, which are then judiciously packaged on a PCB so as to minimize the switching cell stray inductance and the impact of voltage variations (dv/dt) across the common-mode stray capacitance of the assembly. The static and the dynamic operating modes of the proposed multiterminal power chips were validated using 2-D-Sentaurus TCAD simulations. The realized chips were packaged on a PCB to realize both classical and three-chip-based H-bridge inverters. First characterization results validate the electrical operating modes of the H-bridge inverter realized according to the three-chip approach. [ABSTRACT FROM AUTHOR]

This paper deals with the monolithic integration of a multiphase generic static power converter (dc/ac or ac/dc). The integration aims at minimizing wire bonds in order to improve the electrical performance as well as the reliability of power converters. To that end, three multiterminal monolithic power Si chips are devised and extensively studied by 2-D simulations. The first power chip integrates the reverse-conducting IGBT devices that compose the high-side part of the converter circuit. This chip is called the common anode and is validated through experimental realizations. The second power chip integrates the reverse-conducting IGBT devices that compose the low-side part of the converter. This chip is called the common cathode chip. The common anode and cathode power chips are judiciously packaged on a Printed Circuit Board substrate over which an insulating Kapton film is laid and through which window openings are realized. The partial flip-chip packaging, of the two power chips, enables the realization of a compact power H-bridge converter with the lowest stray inductance. The third chip integrates the power converter within a single silicon chip and, consequently, eliminates wire bonds. It is considered as the ultimate integration approach. The latter is validated on a monolithic H-bridge inverter by using Sentaurus mixed-mode 2-D numerical simulations. [ABSTRACT FROM AUTHOR]