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Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules, ideally in a non-destructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions, or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x-rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses has not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits, with past work delivering 20–40 nm resolution on thinned ICs. We describe a simple model for estimating the required exposure, and use it to estimate the future potential for this technique. Here we show for the first time that this approach can be used to image circuit detail through an unprocessed 300 μm thick silicon wafer, with sub-20 nm detail clearly resolved after mechanical polishing to 240 μm thickness was used to eliminate image contrast caused by Si wafer surface scratches. By using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire non-etched ICs to be imaged to 10 nm resolution or better while maintaining their ability to function in electrical tests.

We report several cases of two photon absorption (TPA) laser assisted device alteration (LADA) using continuous wave (CW) 1,340 nm laser in Si Complimentary Metal-Oxide Semiconductor (CMOS) Integrated Circuits (IC). Two photon absorption using CW 1,340 nm laser in Si was confirmed by photon beam induced photocurrent measurements. TPA LADA showed greater than two times better resolution in critical timing circuit defect localization and debug application, when compared with traditional single photon absorption (SPA) LADA with CW 1,064 nm laser. A simplified analysis on the resolution improvements presented here showed in good agreement with our experimental observations. Further enhancements of this technology are outlined, which we believe will enable this technology for critical timing circuit debug capabilities well into the future generations of Si CMOS Debug applications.

Single probe beam phase-sensitive detection has been applied to backside optical probing using an interferometer with a novel vibration cancellation scheme. Improved waveform quality and consistency, compared to amplitude-sensitive detection, has been successfully demonstrated on a number of CMOS microprocessors based on the 0.18 um logic process technology. The interferometric probing scheme will be described in detail and results will be presented.

Liquid immersion lens technology has been applied to internal-node, through-silicon probing of 130 nm integrated circuits. A 100×, 1.3 numerical aperture (NA) objective with 100 μm working distance was specifically designed for this application. An optical resolution of 500 nm is achieved using 1064 nm wavelength light, ≈30% improvement over the standard, air immersion, 0.85 NA lens currently used. Significant improvements in wave form quality were also achieved. A >2× signal to noise ratio improvement is demonstrated on 130 nm technology devices. Probing of 90 nm technology devices indicate that laser voltage probing with liquid immersion lens technology and phase-sensitive detection is extensible to this process node.