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Short-loop process monitoring structures (usually simple device I-V, C-V measurements made after M1 fabrication) are commonly put in wafer scribelines. These test structures are almost always design independent and measured or monitored by the foundry to keep track of process deviations. We propose a design-dependent process monitoring strategy that can accurately predict design performance based on Ieff-based delay and Ioff-based leakage power estimates. Further, we use the predicted delay and power for early yield estimation to: 1) prune bad wafers to save test and back-end manufacturing costs, and 2) prune bad dies to save testing costs. Combining chip pruning with wafer pruning, we can reduce the cost per good chip by up to 13%. Such design-dependent process monitoring can help reduce process optimization effort, and enable quicker yield ramp besides saving testing and manufacturing costs. [ABSTRACT FROM PUBLISHER]

With the increase of the complexity of circuits, fast estimation can provide some vital information for optimal layout decisions. Fast congestion prediction plays an important role in the physical layout of VLSI design. In this paper, we present a probabilistic estimation approach with via minimization constraints. Our model is more realistic than previous models. It has more flexibility for wires to have more usage area to bypass congested regions and blockages. The experiment on routing benchmarks demonstrates the effectiveness of our approach. [ABSTRACT FROM AUTHOR]

Abstract: Congestion estimation is an important issue for design automation of the VLSI layout. Fast congestion estimation provides an efficient means to adjust the placement and wire planning. A probabilistic model of interconnections enables designers to quickly predict routing congestion. We propose a powerful and fast estimation approach that allows wires to have bounded-length detours to bypass congestions. The method is more realistic and precise than the previous work. The experimental results demonstrate the effectiveness of the method on routing benchmarks. [Copyright &y& Elsevier]

Abstract: Congestion estimation plays an important role in the physical layout of VLSI design. This paper presents a new probabilistic estimation model that improves the previous estimators by relaxing the constraint on detours in a route. The model is more general and realistic for it gives the flexibility for the wires to have wider usage area to bypass the congestion regions and blockages. Given a routing grid and a set of nets to be routed, the model predicts the routing density on each edge of the grid. The routing density provides direct congestion estimation. We compare our estimation results to the actual routing results. Experimental results show the effectiveness of our estimator. [Copyright &y& Elsevier]