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Digital signal processing is finding uses in products that do not involve such traditional applications as radar. The chips are generally faster, less costly, and even easier to use. DSP ICs are surfacing in systems that address everything from the more conventional filtering applications to some less traditional ones, like financial modeling and servo-control applications. Some basics on digital-signal-processing products are reviewed in the first of a four-part series.

A design for an integrated circuit that performs a GO/NO-GO test on a 4164 dynamic RAM is presented. The device continuously alternates 1s and 0s through a ZIF-socketed unit, verifying the integrity of all data locations on the DRAM chip. Two eight-bit counters drive the address lines of the unit under test. Microcoded, reduced Boolean equations form a state machine for driving multiplexed address lines. Special terms bypass the initial DRAM read/verify operation until at least one write cycle has occurred and valid data is written at each address. The test circuit reads a single DRAM location, verifies the accuracy of the data bit, writes data of opposite polarity to the same address location, and reads its location to verify that proper toggling took place., The digital circuit shown in Fig 1 performs a GO/NOGO test on a 4164 dynamic RAM (DRAM) by continuously alternating 1s and 0s through the ZIF-socketed unit under test, IC.sub.1. [...]

When choosing a digital signal processor (DSP) chip, it is important to consider interrupts, memory architectures, I-O control, and fixed- or floating-point math. DSP ICs use a Harvard-type architecture, in which program memory and data are separate. Some DSP manufacturers provide one address and one data bus for all communication with memory and I-O chips, while others provide separate buses to control separate data and instruction memories. The trade off is simplicity versus more information to the CPU per time period. Many DSP chips use pipelining to maintain high processing speed, but inherent delay is troublesome to programmers.

Systems with digital signal processing (DSP) microprocessors can be enhanced to handle touchtone dialing and decoding to allow the use of a touchtone telephone as a data entry terminal. The specific DSP microprocessor used in such an application is the TMS32010. The algorithm used for tone generation initializes the processor. The decoder, which continually processes signal samples, can test decoder tapes of test tones. CAPTION: (Tone generation and tone decoding programs.)

This is Part II of a two-part series. Part I described how to build a simple system as a way of learning more about the operation of digital signal processing (DSP) chips in industrial-control applications. Part II describes the breadboard system that links these and other components. The initial breadboard system is laid out openly in an diagram, supported by descriptive text. The board that interfaces the host to the backplane of the breadboard system is explained and illustrated. A block diagram details the system's memory board, described in the text. A circuit diagram shows that the DSP board carries the 32010 muP and only a few other components. A 2-port RAM unites the 320 DSP chip and the host muP. The free space will be used in future experimentation by the author.

The duty cycle of a digital signal can be monitored with a circuit that displays the signal. The circuit can select either a 250 hertz to 2.5 kilohertz range with plus or minus one percent accuracy or a two kilohertz to fifty kilohertz range with plus or minus ten percent accuracy. A circuit diagram of the hardware monitor is included.

Part one of a two-part beginner's guide explains the use of simulators and test vectors. To determine logic array designs correctly, accurate input vectors are required to drive logic simulators. The simulator uses the net list of the logic array and the input vectors. The input vectors can be in waveform format or tabular format. The purpose of simulation vectors is to validate a logic function. Operating conditions can increase propagation delays. Propagation delays for data paths are produced by a timing verification simulation. A simulation at full speed under worst case operating conditions can determine if a part will perform as designed. A circuit diagram of an example circuit; diagrams of a waveform format, vector development, data lines, circuit delays, timing, and data bus contention and a table of the tabular format are included.

Some simple circuitry and a dual universal asynchronous receiver-transmitter (UART) can be used to design a network with local buffering. The network consists of a bus using a multidrop mode of operation with electrical signal conforming to RS422 and RS232C standards. The MC68681 dual UART has two independent UART sections capable of operating at 1M bytes per second. The hardware uses a serial interface with arbitration. The message protocol has a means of detecting collisions. It operates at 125,000 bps, but file transfer times will increase with the number of users. A circuit diagram of a serial interface, a block diagram of an UART, and diagrams of terminal configurations, network topology, and network control are included.

Digital signal processing within TV receivers has been in existence for about two years. This process ultimately leads to longer-term stability within the equipment as well as greater stability in the setup and alignment. Computer control of the sets is as extensive as the digital portions of the equipment. Completely digitized sets must also implement computer control, and which several chips are on the market to handle these functions. For instance, ITT Intermetall is marketing the Digit 2000 IC set that allows construction of a computer-controlled single- or multistandard TV reveiver that's easily manufactured and aligned. A block diagram of one such TV is included.

Semiconductor suppliers will carry a variety of low-cost digital-signal-processing (DSP) devices in the next few years. These devices will enable the user to implement high-speed signal-processing applications at low cost. The advanced capbilities and high performance of these third-generation DSP chips will allow even less-experienced engineers to design them into their products. Possible future suppliers of single-chip DSPs are listed. The DSP industry is moving toward faster instruction cycles and future enhancement of on-chip DSP features. Continuation of the 'Harvard style' of DSP chips, with the pogram side separate from the data side, is expected. Photographs of various chips, a table of manufacturers, a diagrammatic model of the architecture of the DSP-128 from STC Components, and a chart presenting the horizontal lifeline of various chips indicating progress in the state-of-the-art are included. An inset describes present and future DSP devices.

The DSP128 is a cascadable real-time integrated signal processor from STC Components Ltd. Featuring a Harvard architecture, a DMA controller, and a 32-bit multiplier, the chip can process double-precision results in half the time that it takes conventional digital signal processors. Its off-chip memory increases the chip area available for temporary storage of data, thus contributing to its ability to execute a 64-point radix-2 decimation-in-time FFT in only 1.5-MS. Block diagrams of chip operation are included, as well as a program listing of the execution of a 64-point complex FFT.

A family of digital signal-processing chips has been released by Gould AMI. Dubbed the S28211 Series, the family of devices contains chips that feature customizable ROM, 32-point complex FFT operations, ROM filter and utility routines, and a ROM-less chip that allows off-chip memory to be used. The chips are priced at $75 each.

Designers of computer systems can take many diverse routes to process signals. Once restricted to von Neumann architecture, new techniques such as pipelining or the Harvard architecture are now available. These newer architectures usually always result in gross improvements in processing speed, despite drastic improvements in von Neumann type ICs. Array processing is the best choice when doing one operation on large amounts of data. After the array pipeline is filled, the same operation can then be carried out on many data words simultaneously. Chips are available that actually contain four processors that execute the same instruction simultaneously. A glossary of terms is provided.

Analog Devices has developed a family of four CMOS 16-Bit slices that has been designed to deliver all functions necessary for a high performance digital signal processor. The first member is the ADSP-1401, a microprogram sequencer with a 90-ns minimum cycle time. The ADSP-1410 is a fast general purpose data address generator that features a 70-ns cycle time. Filling a high performance design void, the ADSP-1201 handles arithmetic, logic, and shifting. The last member of the family is the ADSP-1101, an enhanced multiplier and accumulator.

Analog Devices is offering a new IC family that is optimized for digital signal processing. Low level concerns about SSI enhancements are eliminated, leaving the designer to worry about speed, precision, and architectural structure. The fast Fourier transform serves as the basis of performance for the set, and thanks to the chip set's built-in functions, a compact digital signal processor can be constructed with an enhanced multiplier and accumulator (EMAC) chip. Operating at 10MHZ, the system can compute a 1-kpoint complex FFT in 3ms.