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A novel sub-threshold 9 T Static Random Access Memory (SRAM) cell designed and simulated in 14-nm FinFET technology is proposed in this paper. The proposed 9 T-SRAM cell offers an improved access time in comparison to the 8 T-SRAM cell. Furthermore, an assist circuit is proposed by which the leakage current of the proposed SRAM cell is reduced by 20% when holding '0' and an equal leakage current during hold '1' in comparison to the 8 T-SRAM cell. The proposed circuit improves the access time by 40% in comparison to the 8 T-SRAM cell without any degradation in write and read noise margins, as well. The maximum operating frequency of the proposed SRAM cell is 1.53 MHz at VDD = 270 mV. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

We investigate the impact of wire geometry on the resistance, capacitance, and RC delay of Cu/low- $k$ damascene interconnects for fixed line-to-line pitch. The resistance is computed by applying a semiempirical resistivity model, calibrated to Cu damascene wires, integrated with a Ru-based liner, currently investigated for the 7 nm logic technology node. The capacitance is simulated by means of a 2D field solver (Raphael) by Synopsys. The impact of line dimensions is analyzed for the case of 32 nm pitch interconnects, which are representative of the 7 nm logic technology node. We show that for aspect ratios greater than 1, the resistance is more sensitive to variations of the line width rather than of the line height, because of the higher surface scattering induced by the sidewall interfaces, which are closer to each other compared with the top and bottom interfaces. For capacitance, low- $k$ sidewall damage exacerbates capacitance sensitivity to line dimensions and, for typical interconnect schemes, the impact of line width variations dominates over variations of the line height. We demonstrate that for a given pitch and dielectric stack height, the RC delay can be significantly reduced by targeting wider and deeper damascene trenches, that is, by trading capacitance for resistance, and that an optimal wire geometry for RC delay minimization exists. In addition, we show that a given RC delay can be achieved with several geometries and, therefore, $R$ and $C$ pairs, which represents a useful degree of freedom for designers to optimize system-level performance. As an application, we analyze a possible 7 nm technology scenario and show that wide and deep damascene trenches can mitigate the impact of the increased wire resistance on circuit delay. [ABSTRACT FROM AUTHOR]

Based on realistic circuit- and system-level simulations, graphene interconnects are analyzed in terms of multiple material properties, such as the mean free path (MFP), the contact resistance, and the edge roughness. The benchmarking results indicate that the advantage of using graphene interconnects occurs only under certain circumstances. The device-level parameters, including the supply and threshold voltages, and the circuit-level parameters, including the wire length and width, have large impacts on both the delay and energy-delay product (EDP). At the circuit level, one representative circuit, a 32-bit adder, is investigated, where up to 40% and 70% improvements in delay and EDP are observed. At the system-level analysis, an ARM Cortex-M0 processor is synthesized, and placement and routing are performed. After replacing copper interconnects with multilayer graphene interconnects, up to 15% and 22% performance improvements in clock frequency and EDP have been observed. It is also demonstrated that the benefits of using graphene for the ARM core processor are strongly dependent on the quality of the graphene, such as the MFP and the edge roughness. [ABSTRACT FROM AUTHOR]

Abstract: With the growth of the embedded devices consumer market, power efficient hardware is needed. Therefore power-aware architectural exploration is one of the most crucial design steps. For such an exploration procedure, it is important to accurately model the power consumption of all main components of the embedded system. Registers and register files are one of the highest power consumers of any programmable processor, but there is a lack of accurate and publicly available models. This paper provides such a power model for standard cell based register files for 130 and 90nm technologies. The proposed model provides dynamic power, leakage power, area and timing information for register files in terms of key parameters like width, depth, activity, ports, and capacitive loading. It is shown that current models capture neither correct absolute nor relative trends present in register files. It is shown that some key, but often neglected parameters like switching activity, load have a larger influence in some particular sizes of the register files than others. Therefore, using the Empire model, accurate architectural exploration is possible. [Copyright &y& Elsevier]

Modern portable embedded devices require processors that can provide sufficient performance for demanding multimedia and wire- less applications. At the same time they have to be flexible to support a wide range of products and extremely energy efficient to provide a long battery life. Coarse Grained Reconfigurable Architectures (CGRAs) potentially meet these constraints by providing a mix of flexible computational resources and large amounts of programmable interconnect. The vast design space of CGRAs complicates the development of optimized processors. Most effort has been spent on improving the performance. However, the energy cost of the programmable interconnect is becoming more expensive and this cost can no longer be neglected. In this work we present an energy- and performance-aware exploration for the interconnect of a CGRA and show that important tradeoffs can be made for those metrics. This will en- able designers to develop more efficient architectures, tuned to a targeted application domain. [ABSTRACT FROM AUTHOR]

An exploratory modeling methodology is presented for estimating power noise in advanced technology nodes. The models are evaluated for 14, 10, and 7 nm FinFET technologies to assess the impact on performance. The power noise is composed of three parts, noise related to the global power grids, via stacks, and local power rails, based on the hierarchical nature of power distribution networks. In 14 nm technology, the global power noise dominates the total power noise. The power noise is lower and more evenly distributed in 10 nm technology. 7 nm technology is shown to be more sensitive to local power noise. To decrease the global power noise, extra metal layers are added to the global power grid. A 75% reduction in global power noise is observed in 14 nm technology. Stripes between local track rails are evaluated to reduce the local power noise, exhibiting up to 57% improvement in local power noise at the 7 nm technology node. As a promising alternative material for power network interconnects, few layer graphene is shown to exhibit good potential for reducing local power noise. The effects of different scaling scenarios of the local power rails on power noise are also discussed. [ABSTRACT FROM AUTHOR]

Negative Bias Temperature Instability (NBTI) is one of the major time-dependent degradation mechanisms that impact the reliability of advanced deeply scaled CMOS technologies. NBTI can cause workload-dependent shifts on a transistor’s threshold voltage ( V TH ), and performance during its lifetime. This study presents a comparison of the NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes. The first part of the study focuses on the NBTI-induced performance degradation of 32-bit adders (one of the most fundamental block of a processor’s arithmetic logic unit) from the points of architectural topology and workload dependency in the planar technologies (i.e. commercial 28 , 45 , 65 nm nodes), while the second part investigates the energy-delay product degradation of ring oscillators beyond the planar nodes (i.e. research-grade 14 , 10 , 7 nm FinFET technology nodes for several FET channel materials, e.g. Si, SiGe, Ge, InGaAs). Results show the tight coupling between the NBTI aging and the architectural topology, run-time workload, and technology choice. [ABSTRACT FROM AUTHOR]