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This brief demonstrates a fully contactless wafer-level testing based on UHF radio identification (RFID) technology enriched by high-quality on-chip antenna. The antenna, which uses exactly the same tag IC area (i.e., 0.45 mm2), exploits a low-cost post-process consisting of a thick dielectric layer and a copper metal, thus significantly improving the quality factor with respect to a standard CMOS implementation. Contactless wafer-level testing of a tag array is performed by simultaneous inductive coupling with a customized near-field reader. With a 27-dBm standard UHF RFID reader, a reading range up to 2.5 mm is demonstrated at 865 MHz. Anti-collision algorithm and memorized x–y device coordinates allow IC identification on the wafer under test to be achieved. Thanks to its cost-effectiveness, the proposed approach can be easily extended to general purpose IC contactless testing. [ABSTRACT FROM AUTHOR]

This paper presents a Colpitts-based voltage-controlled oscillator (VCO) for W-band radar applications. In the proposed circuit, the oscillation signal is directly drawn from the switching transistor bases by means of the primary winding of a transformer tank, while the secondary winding drives the output buffer. This solution improves both tuning range and oscillation swing with respect to traditional millimeter-wave VCO topologies without increasing power supply. The oscillator is implemented in a 0.13-\mu\ m SiGe BiCMOS technology, along with high-frequency dividers to enable low-frequency testing. The VCO exhibits a phase noise of -\99.3 dBc/Hz at 1-MHz offset from an oscillation frequency of 76 GHz and a tuning range of 4.9% with a consumption of 65 mW at 2.5-V power supply. The VCO is also used to drive a two-stage power amplifier in a fully integrated W-band transmitter that is able to deliver an overall output power as high as 15 dBm at 76 GHz. [ABSTRACT FROM AUTHOR]

This paper presents a 15-dBm power amplifier for 77-GHz automotive radar applications, which is fabricated in a 0.13-\mu\ m SiGe:C BiCMOS process featuring bipolar transistors with f T / f\max of 230/280 GHz. The circuit consists of a two-stage pseudodifferential cascode with fully integrated input/output matching networks. State-of-art performance is achieved with the proposed design algorithm and layout optimization. The amplifier demonstrates a figure-of-merit of 2500 achieving a 22.5-dB power gain and a power-added efficiency of 7.5% at 77 GHz, while drawing 130 mA from a 2.5-V voltage supply. [ABSTRACT FROM AUTHOR]

n amplifier topology based on a transformer-coupled cascode stage is presented and compared with the most used solutions for sub-μm CMOS power amplifiers, which are the common-source stage, cascode stage, and capacitive-coupled cascode stage. The comparison was carried out by designing each amplifier in a 65-nm CMOS technology and for a 60-GHz operating frequency. The design was optimized for a trade off among power gain, saturated output power, and linearity. Operating from a 1.2-V supply voltage, the proposed amplifier improves both small-signal and large-signal performance with respect to the most common approaches, thus demonstrating effectiveness with sub-μm CMOS technologies and mm-wave operation. [ABSTRACT FROM AUTHOR]

A lumped scalable model of silicon integrated inductors for RF IC design is presented. It was validated up to 20 GHz using measured performance parameters of more than 70 single-ended and differentially driven spirals covering 0.2- to 8.3 nH inductance values. Excellent accuracy, full geometrical scalability, compactness and high capability for implementation in circuit simulators promote the proposed model as a reliable time-saving design tool. Two circuital example, i.e., 5-GHz down-converter and 10-GHz VCO, are also presented to demonstrate its use in practical cases. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009. [ABSTRACT FROM AUTHOR]

This paper reviews state-of-the-art architectures for galvanically isolated DC-DC converters with data transmission for low-power applications. Such applications do not have stringent requirements, in terms of power efficiency, but ask for very compact, highly integrated implementations. To this aim, architecture simplicity is crucial, especially when data transmission and/or output power regulation are required. Since the bottleneck of galvanically isolated systems is the isolation device (i.e., typically a stacked thick oxide or polyimide transformer), the reduction of the number of isolated links, while preserving both power and data functionalities, is the more effective strategy to increase the level of integration, reduce the form factor, and have a lower cost per channel. Specifically, this review compares the pros and cons of different architectures that address this challenge differently from traditional solutions. [ABSTRACT FROM AUTHOR]

The analysis and modeling of monolithic stacked transformers fabricated in a high-speed silicon bipolar technology is addressed. On-wafer experimental measurements are employed to investigate the effect of layout scaling on transformer performance parameters (i.e., self-resonance frequency, magnetic coupling coefficient, and insertion loss). Based on this analysis, a wideband lumped model is developed, whose parameters are related to layout and technological data through closed-form expressions. Model accuracy is demonstrated by comparing simulated and measured S-parameters, coil inductance, magnetic coupling coefficient, and maximum available gain of several transformers with scaled layout geometry. The self-resonance frequency is also employed as a figure-of-merit to demonstrate model accuracy at very high frequency. [ABSTRACT FROM AUTHOR]

This paper reviews state-of-the-art approaches for galvanically isolated DC-DC converters based on radio frequency (RF) micro-transformer coupling. Isolation technology, integration level and fabrication issues are analyzed to highlight the pros and cons of fully integrated (i.e., two chips) and multichip systems-in-package (SiP) implementations. Specifically, two different basic isolation technologies are compared, which exploit thick-oxide integrated and polyimide standalone transformers, respectively. To this aim, previously available results achieved on a fully integrated isolation technology (i.e., thick-oxide integrated transformer) are compared with the experimental performance of a DC-DC converter for 20-V gate driver applications, specifically designed and implemented by exploiting a stand-alone polyimide transformer. The comparison highlights that similar performance in terms of power efficiency can be achieved at lower output power levels (i.e., about 200 mW), while the fully integrated approach is more effective at higher power levels with a better power density. On the other hand, the stand-alone polyimide transformer approach allows higher technology flexibility for the active circuitry while being less expensive and suitable for reinforced isolation. [ABSTRACT FROM AUTHOR]

Growing importance of wireless communication systems forces reduction of power consumption of the designed integrated circuits. The paper focuses on minimization of power consumption in a digitally controlled oscillator (DCO) that can be employed as oscillator in GPS/Galileo receiver. The new hybrid architecture of DCO combines good phase noise performance of a Colpitts oscillator and relaxed startup conditions of a cross-coupled differential pair oscillator. The proposed new DCO generates a quadrature signal in a current reused frequency divider. Such solution allows of the dissipated power to be reduced. The DCO has been implemented in 110 nm CMOS technology. It generates output signal in frequency range from 1.52 GHz to 1.6 GHz and consumes 1.1 mW from 1.5 V supply voltage. The measured phase noise equals −116 dBc/Hz at 1 MHz offset from 1.575 GHz output signal. [ABSTRACT FROM AUTHOR]

This paper exploits an effective approach to overcome the breakdown limitations of traditional galvanic isolators based on chip-scale isolation barriers, thus achieving a very high isolation rating (i.e., compliant with the reinforced isolation requirements). Such an approach is based on radio frequency (RF) planar coupling between two side-by-side co-packaged chips. Standard packaging along with proper assembling techniques can be profitably used to go beyond 20-kV surge voltage without using expensive or exotic isolation components. As a proof of concept, a bidirectional data transfer system based on RF planar coupling able to withstand an isolation rating as high as 25 kV has been designed in a low-cost standard 0.35-µm CMOS technology. Experimental measurements demonstrated a maximum data rate of 40 Mbit/s using a carrier frequency of about 1 GHz. The adopted approach also guarantees a common mode transient immunity (CMTI) of 250 kV/µs, which is a first-rate performance in view of next generation galvanic isolators for wide-bandgap power semiconductor devices, such as gallium nitride high-electron mobility transistors (GaN HEMTs) and silicon carbide (SiC) MOSFETs. [ABSTRACT FROM AUTHOR]

Abstract This work presents a review of integrated transformers for galvanic isolation with particular focus on their modelling in power transfer systems. A comparison between transformer-coupled oscillator topologies is carried out, highlighting the main differences in the realization of the isolation transformers. Lumped geometrically scalable modelling of the most adopted isolation transformer topologies are presented and compared. Transformer models have been validated by means of electromagnetic simulations in a wide range of geometrical parameters, achieving absolute errors lower than 12% for inductance, Q -factor peak, self-resonance frequency, and magnetic coupling factor. Highlights • A review of integrated transformers for galvanically isolated dc-dc converters. • Scalable lumped models of three different transformer configurations are compared. • The results can be exploited within an iterative co-design procedure. [ABSTRACT FROM AUTHOR]