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A scalable compact model for SCR-based electrostatic discharge (ESD) protection devices is presented. This model captures the effect that layout spacing has on SCR characteristics, such as holding voltage and trigger current. The model also captures both the delayed turn-on of the SCR, which results in large voltage overshoots during fast rise-time ESD events and the charge removal mechanisms that underlie the turn-off transient. Bias and time dependences of SCR on-resistance are captured with a resistance model that accounts for self-heating. [ABSTRACT FROM AUTHOR]

Abstract: A model is presented for external latchup. The effects of spacing, temperature, supply voltage and layout are captured in the model. The model shows a good fit to measurement results from two different technologies, RF-CMOS and SmartMOS. [Copyright &y& Elsevier]

The reliability of very thin gate oxide under electrostatic discharge-like pulse stress is investigated. Time-dependent dielectric break- down of gate oxide with thicknesses ranging from 2.2 to 4.7 nm is characterized down to the nanosecond lime regime. The l/E model best fits the time-to-breakdown data. Self-heating does not need to be incorporated into the time-to-breakdown model. The oxide trap generation rate is a function of the stress pulse-width for nanosecond and microsecond stress pulses. [ABSTRACT FROM AUTHOR]