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In this study, a three-level static RAM cell with a single BL based on 16 nm BWG CNFET technology is proposed for use in high-performance IoT platforms. The proposed memory structure in a bit-interleaved architecture compatible design consists of a standard triple buffer gate (STB) based on the BWG CN-TGDI method and a pair of transmission gates as an access network. In the STB cell structure, the threshold voltage calibration by the flat band voltage parameter of the CNTs has been used to improve the static noise margin at logic level '1'. In addition, pseudo-resistor and stacked transistor structures have been used to control the single static current path during logic level '1' generation and cell leakage current, respectively. The simulation results based on the Monte Carlo method show that the hardware performance parameters PDP and EDP for the proposed design have been improved by 38.8% and 31%, respectively, compared to the counterpart structure. Moreover, the proposed architecture has shown a more reasonable result in terms of noise immunity than the best-performing design by 1.93 times. Finally, to investigate a real-world application, the triple memory structure has been used to store the colored QR code image with the data content of three values using the proposed hardware algorithm. The obtained results for the quality evaluation metrics, PSNR and MSSIM, emphasize the suitability of the proposed memory architecture for the development of next-generation SoCs. [ABSTRACT FROM AUTHOR]

This paper presents a one‐sided 10‐transistors static‐random access memory (SRAM) cell appropriate for the internet of things (IoT) applications in which energy‐efficient SRAM cells are necessary to raise the battery lifetime. The bit‐cell core of the proposed SRAM cell is composed of two inverters with different structures based on the gate‐wrap‐around (GWA) carbon nanotube (CNT)‐gate‐diffusion input (GDI) technique and only one‐bit line to perform both read and write operations to minimize active power consumption. The proposed bit‐cell uses a transmission gate network and write‐assist schemes to significantly improve the write‐ability and stack read‐decoupling technique to enhance hold‐/read‐stability. Moreover, a memory mini‐array has been implemented using the proposed cell along with all the principal circuitries. Extensive Monte Carlo (MC) simulations show that write/hold/read static noise margins (SNMs) are improved by about 1.252, 1.196, and 1.152 times, respectively. Also, the results of evaluating the write‐ and read‐yield parameters for the proposed SRAM bit‐cell are about 22% and 13% better than counterpart bit‐cell designs, respectively. In addition, the bit error rate (BER) and energy dissipation parameters for the proposed memory cell are almost 61% and seven times higher than the studied SRAM bit‐cell in the same simulation process. Finally, to evaluate the effectiveness of the proposed SRAM bit‐cell in the real‐world application, a memory array architecture with an online (or off‐chip) adaptive power supply voltage based on a hardware algorithm for storing digital images at a minimum energy dissipation is proposed. Our simulation results emphasize that the proposed memory array can be a good candidate for energy‐efficient and noise‐immunity IoT platforms. [ABSTRACT FROM AUTHOR]