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The annealing behavior of a lanthanum oxide thin film deposited on a silicon (001) substrate by electron-beam evaporation has been studied by aberration-corrected transmission electron microscopy (TEM), scanning TEM (STEM), and electron energy loss spectroscopy (EELS). We have developed a procedure for the precise measurement of thickness and interfacial roughness by taking advantage of features of aberration correction combined with the statistics of fluctuating crystalline edge positions. The results of the measurements and quantitative elemental analyses by STEM-EELS have revealed atomic diffusion and reactions during deposition and postdeposition annealing (PDA) at 300 and 500 °C. The channel mobility could be limited by Coulomb scattering before PDA, and by remote roughness scattering and remote phonon scattering after PDA at 500 °C. When we consider the large leakage current caused by oxygen defects in the as-deposited sample and the large equivalent oxide thickness of the thick Si-rich layer in the 500 °C-PDA sample, the gate properties of the 300 °C-PDA sample should be better than those of other samples, as shown by electrical measurements. [ABSTRACT FROM AUTHOR]

Abstract: This study reports on the electrical characteristics of (110)-oriented nMOSFETs with a direct contact La-silicate/Si interface structure and the detailed comparison with (100)-oriented nMOSFETs. Precise control of oxygen partial pressure can provide the scaled EOT down to 0.73nm on (110) orientation in common with (100) orientation. No frequency dispersion in C gc–V characteristic for (110)-oriented nMOSFETs is successfully demonstrated at scaled EOT region, while higher amount of available bonds on (110) surface results in a larger interface state density, leading to the degradation of sub-threshold slope. High breakdown voltages of 2.85V and 2.9V for (100)- and (110)-oriented nMOSFETs are considered to be due to superior interfacial property. The electron mobility on (110) orientation is lower than that on (100) orientation because of the smaller energy split between fourfold valleys and twofold valleys as well as the larger density of states for lower-energy valleys in the (110) surface. Moreover, electron mobility is reduced with decreasing EOT in both (100)- and (110)-oriented nMOSFETs. It is found that threshold voltage instability by positive bias stress is mainly responsible for bulk trapping of electron even with a larger interface state density in (110) orientation and influence of surface orientation on threshold voltage instability is negligibly small. [Copyright &y& Elsevier]

Abstract: The roll-off and roll-up behavior of flatband voltage (V fb) on equivalent oxide thickness (EOT) of La2O3/silicate capacitors have been characterized by X-ray photoelectron spectroscopy and modeled by the fixed charges. It has been revealed that the thickness of the reactively formed silicate layer is dependent on the La2O3 thickness initially deposited on the wafer. When the La2O3 thickness is over 3nm, the silicate layer has been found to be formed with a constant thickness of 1.6nm. However, while decreasing the La2O3 thickness to 1nm, the thickness of silicate layer decreases due to the reduction of radical oxygen atoms originated from the La2O3 layer, resulting in the formation of La-rich silicate. The V fb roll-off behavior can be attributed to the enhanced generation of positive fixed charges induced by the diffusion of metal atoms from the gate electrode into the silicate layer. On the other hand, the V fb roll-up behavior can be explained when the initially deposited La2O3 layer has been all converted into silicate. [Copyright &y& Elsevier]

Abstract: Chemical bonding states and electrical characteristics of a La-silicate formed as a compositional transition layer at La2O3/Si interface has been examined. A direct contact of a high-k gate dielectric with Si substrate has been achieved without forming SiO2-based interfacial layer by forming a compositionally graded La-silicate layer, which is advantageous for equivalent oxide thickness (EOT) scaling. A transistor operation with an EOT of 0.48nm has been demonstrated with low temperature annealing, however a degradation of effective mobility (μ eff) has been observed. A high μ eff of 300cm2/Vs with relatively low interfacial state density (D it) of 1011 cm−2/eV can be achieved when annealed at 500°C, indicating fairly nice interface properties of silicate/Si substrate. Mobility analysis has revealed an additional Coulomb scattering below an EOT of 1.2nm, which is in good agreement with the negative shifts in threshold and flatband voltages. Moreover, increase in D it and subthreshold slope have been observed while decreasing the EOT, suggesting the influence of metal atoms diffused from the gate electrode. A mobility degradation model is proposed using metal induced defects generation. [Copyright &y& Elsevier]

Abstract: The chemical bonding states and electrical characteristics of SrO capped La2O3/CeO x gate dielectric have been examined. Angle-resolved X-ray photoelectron spectroscopy measurement has revealed that Sr atoms diffuse into silicate layer to form SrLa-silicate after annealing. Owing to the incorporation of Sr atoms into silicate layer, a transistor operation with an equivalent oxide thickness (EOT) below 0.5nm has been demonstrated. A strongly degraded effective electron mobility of 78cm2/Vs at 1MV/cm has been obtained, which fit well with the general trend in small EOT range below 1nm. Although process optimization is needed to improve the performance of transistors, Sr capping technique can be useful for EOT scaling. [Copyright &y& Elsevier]

Abstract: The study on post metallization annealing (PMA) in electrical characteristics and interfacial properties of La2O3/Ge structures has been conducted. The PMA treatment in N2 ambient induces the growth of interfacial Ge oxide layer accompanied with decrease of capacitance value and interface trap density. The interface-layer growth is caused by the oxidation of Ge substrate due to the hydroxyl group absorbed in La2O3 from the ambient. The metal electrode capping might prevent the hydroxyl from evaporating during annealing, which enhances the interface reaction. On the other hand, leakage current increment has been observed for the sample with PMA in case of using Pt gate electrode. It is due to the diffusion of Pt and/or Ge and a Pt-germanide formation in La2O3 film during PMA. This leakage current increment can be suppressed by using Ta or W electrode which has less reactivity with Ge than Pt at high temperature. [Copyright &y& Elsevier]

A simple yet accurate model for the postbreakdown output characteristics of advanced n-MOS transistors with metal gate (W) and high-κ (La2O3, equivalent oxide thickness=0.6 nm) gate insulator is reported. The model specifically deals with the so-called linear response regime in which the transistor action is no longer operative after the failure event. By analyzing three particular cases of interest, it is shown that the proposed model is able to account for the conduction characteristics corresponding to failure sites located both at the center of the channel region and close to the source and drain contacts. A compact model for the bulk-drain current is included in order to simulate the departure from linearity occurring at the negative drain bias. [ABSTRACT FROM AUTHOR]

Abstract: This study focuses on studying the effective electron mobility in direct contact La-silicate/Si structure based nMOSFETs and searching for the difference of the mobility characteristics compared with the SiO2 MOSFETs. In this study, three types of gate electrode structure were prepared to investigate the mobility characteristics over a wide EOT range; W for EOT of 1.63nm, TiN/W for EOT of 1.02nm and metal-inserted poly-Si (MIPS) for EOT of 0.71nm. Since the silicate formation is basically caused by the presence of oxygen, Si layer in MIPS can suppress the oxygen in-diffusion from atmosphere, resulting in scaled EOT. It is found that the Eeff dependence of mobility with La-silicate is observed to differ from the mobility of SiO2 MOSFETs. The electron mobility with La-silicate shows the weaker Eeff dependence than the mobility of SiO2 nMOSFETs in middle and high Eeff region. This suggests an existence of additional mobility component related to the direct contact La-silicate/Si structure. The effective electron mobility is degraded with decreasing EOT in entire Eeff region. This means that the scattering sources including Coulomb scattering, phonon scattering and surface roughness scattering are located not at La-silicate/Si interface but the inside of gate stacks and approach the Si inversion channel. Coulomb scattering and phonon scattering are thought to be strengthened by increasing k-value because of the enhancement of Coulomb scattering potential and higher ionicity in La-silicate gate dielectrics. The influence of metal/high-k interface is also considered to affect on the mobility with decreasing the EOT. [Copyright &y& Elsevier]

Abstract: This work reports a novel method for improving the electrical properties of lanthanum gate oxide (La2O3) by using aluminum doping and rapid thermal annealing (RTA) techniques. In the bulk of the Al-doped La2O3 film together with 600 °C RTA, we found that the aluminum atoms were incorporated into the oxide network and the film was transformed into lanthanum aluminate complex oxide. At the interface, a thin Al2O3 layer was formed. This interfacial Al2O3 layer suppressed the out-diffusion of substrate Si, the formation of interfacial silicate layer and silicide bonds. These effects resulted in a significant reduction on the bulk and interface trap densities and hence the gate leakage current. [Copyright &y& Elsevier]

Abstract: The effect of a thin Si layer insertion at W/La2O3 interface on the electrical characteristics of MOS capacitors and transistors is investigated. A suppression in the EOT increase can be obtained with Si insertion, indicating the inhibition of diffusion of oxygen atoms into La2O3 layer by forming an amorphous La-silicate layer at the W/La2O3 interface. In addition, positive shifts in V fb and V th caused by Si insertion implies the formation of amorphous La-silicate layer at the top of La2O3 dielectrics reduces the positive fixed charges induced by the metal electrode. Consequently, a large improvement in mobility has been confirmed for both at peak value and at high E eff of 1MV/cm with Si inserted nFETs. Although a degradation trend on EOT scaling has been observed, the insertion of thin Si layer is effective in pushing the scaling limit. [Copyright &y& Elsevier]

Abstract: A novel interpretation for conductance spectra obtained by conductance method of La2O3 gated MOS capacitors has been proposed. Two distinct peaks, one with broad spectrum ranging from 10k to 200kHz and the other near 1kHz with a single time constant spectrum, have been observed at depletion condition. The former spectrum can be assigned as the interface traps (Dit ) located at the interface between La-silicate and the Si substrate by statistical surface potential fluctuation model. On the other hand, as the latter slow trap signal shows strong influence with the thickness of La-silicate layer, it can be assigned as the trappings (Dslow ) at the interface between La2O3 and La-silicate. Finally, the Dit and Dslow trends on annealing temperature are summarized. [Copyright &y& Elsevier]

Abstract: In this work, the effect of nitrogen implantation on thin La2O3 films grown by e-beam evaporation are investigated using x-ray photoelectron spectroscopy (XPS), current–voltage (I–V) and capacitance–voltage (C–V) measurements. The amount of nitrogen incorporation in the oxide film by plasma immersion ion-implantation (PIII) is found to be quite low (about 3% near the surface). However, introduction of nitrogen atoms into La2O3 network results in a significant reduction in the oxide traps and leads to a notable improvement in both material and electrical properties of the dielectric. [Copyright &y& Elsevier]