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Hybrid-type thin-film transistors were fabricated using amorphous oxide and colloidal quantum dots. To prevent damage to the quantum dots, amorphous SIZO, which can be processed at low temperatures, was deposited by RF sputtering. In the case of a general hybrid type device, it is known that the characteristics of a multilayer material are significantly lower than that of a single material, and this is greatly affected by the interface characteristics between each material. The electrical characteristics of a single SIZO TFT, such as threshold voltage, field-effect mobility, on/off current ratio, and subthreshold slope, have been observed as −0.15 V, 9.54 cm2/Vs, 2.9 × 108, and 0.34 V/dec, respectively while electrical characteristics of hybrid-type OQO TFT were observed as 1.39 V, 9.19 cm2/Vs, 3.9 × 108, and 0.35 V/dec, respectively. As a result, it was confirmed that the electrical characteristics did not change significantly when the single SIZO TFT and the hybrid type OQO TFT have been compared in this experiment. Its electrical properties are mainly driven by the upper and lower a-SIZO layers. a-SIZO which has amorphous properties, can provide excellent surface properties because it can completely cover the spherical QD when it comes into contact with the QD. These results are expected to be applicable to many important applications.

In this study, we examine the electrical characteristics of p+–n+–i–n+ silicon-nanowire field-effect transistors with partially gated channels. The silicon-nanowire field-effect transistors operate with barrier height modulation through positive feedback loops of charge carriers triggered by impact ionization. Our field-effect transistors exhibit outstanding switching characteristics, with an on current of ˜10−4 A, an on/off current ratio of ˜106, and a point subthreshold swing of ˜23 mV/dec. Moreover, the devices inhibit ambipolar characteristics because of the use of the partially gated structure and feature the p-channel operation mode.

In this work, we report a fully CMOS-compatible single silicon neuron device, by exploiting interlinked positive and negative feedback loops. The neuron device exhibits the key features of leaky integrate-and-fire functionality and can produce neuronal oscillations that resemble biological oscillations. The stochastic nature and analog input-sensitivity of the feedback switching dynamics are observed in the device. Moreover, the neuronal oscillations of the two-terminal device do not require any power supplied by external bias lines.

In this study, a device design of single-gated feedback field-effect transistors (FBFETs) is proposed to achieve latch-up behaviors with high current gains. The latch-up mechanism is examined by conducting an equivalent circuit analysis, and the band diagram, I–V characteristics, memory window, subthreshold swing, and on/off current ratio are investigated using a commercial device simulator. The proposed FBFETs exhibit memory windows wider than 3.0 V, subthreshold swings less than 0.1 mV/decade, the on/off current ratios of approximately 1010, and on-currents of approximately 10−5 A at room temperature. The superior device characteristics and controllable memory windows open the promising possibility of FBFETs as the next-generation electronic devices.

In this study, we examine the electrical characteristics of silicon nanowire feedback field-effect transistors (FBFETs) with interface trap charges between the channel and gate oxide. The band diagram, I–V characteristics, memory window, and operation were analyzed using a commercial technology computer-aided design simulation. In an n-channel FBFET, the memory window narrows (widens) from 5.47 to 3.59 V (9.24 V), as the density of the positive (negative) trap charges increases. In contrast, in the p-channel FBFET, the memory window widens (narrows) from 5.38 to 7.38 V (4.18 V), as the density of the positive (negative) trap charges increases. Moreover, we investigate the difference in the output drain current based on the interface trap charges during the memory operation.

In this study, we fabricated a 2 × 2 one-transistor static random-access memory (1T-SRAM) cell array comprising single-gated feedback field-effect transistors and examined their operation and memory characteristics. The individual 1T-SRAM cell had a retention time of over 900 s, nondestructive reading characteristics of 10,000 s, and an endurance of 108 cycles. The standby power of the individual 1T-SRAM cell was estimated to be 0.7 pW for holding the “0” state and 6 nW for holding the “1” state. For a selected cell in the 2 × 2 1T-SRAM cell array, nondestructive reading of the memory was conducted without any disturbance in the half-selected cells. This immunity to disturbances validated the reliability of the 1T-SRAM cell array.

In this article, we present a transposable three-transistor static random access memory (3T-SRAM) array consisting of independent double-gate feedback field-effect transistors as binary synaptic devices and access transistors. The synaptic functions of the ${2} \times {2}$ SRAM array are investigated through mixed-mode technology computer-aided design simulations. This 3T-SRAM array provides parallel and bidirectional synaptic updates with fast operating speed. Furthermore, a simplified spike-timing-dependent plasticity learning rule is implemented by adjusting the widths of memory pulses. A compact cell area and a low-leakage power consumption allow this 3T-SRAM array to be used for adaptive synaptic devices in a large-scale neuromorphic system.

We present polarity control of the carrier injection for a feedback field-effect transistor (FBFET) with a selectively thinned p+-i-n+ Si nanowire (SiNW) channel and two separate gates. The SiNW FBFET can be reconfigured in the p- or n-channel operation modes via simple control of electric signals. The two separate gates induce potential barriers in the SiNW channel for selective control of the carrier injection. In contrast to previously reported reconfigurable transistors, our transistor features symmetry of the electrical characteristics for the p- and n-channel operation modes. Positive-feedback operation of the SiNW FBFET provides superior switching characteristics for the p- and n-type configurations, including the on/off ratios (∼ 105) and subthreshold swings (1.36-1.78 mV/dec). This novel transistor is a promising candidate for reconfigurable electronics.

We demonstrate the nonvolatile and volatile memory characteristics of a gate-all-around silicon nanowire feedback field-effect transistor (FBFET) with a nitride charge-storage layer analyzed by a commercial TCAD simulator. Our FBFET exhibits a threshold voltage window of 0.76 V with a programming/erasing time of ${1}~\mu \text{s}$ in the nonvolatile memory mode. We investigated the delay of read operations with accumulated charges in the intrinsic channel region in this memory mode. Moreover, the FBFET exhibits a sensing margin of 6.3 $\mu \text{A}$ and a read/write speed of 10 ns with an outstanding retention time, as well as nondestructive read characteristics in the volatile memory mode, allowing this device to operate without any refresh operation. In addition, we describe the operating principle of our device and demonstrate its potential as integrated memory for 3-D integrations.

The dependency of the inverter voltage gain on the current level (ILevel) of depletion mode (D-mode) thin-film transistors (TFTs) has been investigated with only n-type oxide semiconductor-based TFTs. It is clear that the voltage gain strongly depends on the D-mode ILevel. To investigate the dependency, photo stress was applied to the D-mode TFT to compare the inverter characteristics depending on the D-mode ILevel. As the photo stress time increased, the D-mode ILevel increased, and the voltage gains were degraded as a result. This was mainly because the ILevel of the D-mode is formed in the high section of the subthreshold slope (S.S) of the enhancement mode (E-mode) TFT when the photo stress was applied. By designing an inverter with a low D-mode ILevel, a high voltage gain of 9.85 was obtained at VDD = 3 V. It is important to note that the S.S value of the E-mode and the ILevel of the D-mode should be optimized for high voltage gain for the application of next generation integrated circuits and highly sensitive photodetectors.

On the ZTO system, Si was found to be considered as an oxygen vacancy suppressor due to Si atom having high bonding strength with oxygen. The a-SZTO thin films fabricated with thin-film transistors showed a tendency of decreasing electrical properties as the Si content increased. In addition, various resistances, such as total resistance (Rt), contact resistance (Rc), and sheet resistance (Rsh) depending on Si content were analyzed using transmission line method. It was also found that Rsh was increased due to suppressing oxygen vacancies by Si atom. Threshold voltage can be controlled through simple adjustment of Si content and a NOT logic circuit is fabricated through this. In the fabricated two NOT logic circuits, high voltage gain of 11.86 and 9.23 was obtained at VDD = 5 V, respectively. In addition, we found that even more complex NAND and NOR logic circuits work just like truth tables. Therefore, logic circuits fabricated according to simple Si content can be applied to next generation integrated circuits.

In this study, we investigated the effect of electrode materials on the electrical characteristics of coplanar top-gate a-ITGZO thin-film transistors, in which the gate, source, and drain electrodes were made of the same metal, Ti or Al. The field-effect mobilities of the a-ITGZO thin-film transistors with Ti and Al electrodes were 35.2 and 20.1 cm2/V·s, respectively, and the threshold voltage of the a-ITGZO thin-film transistor with Ti electrodes was −0.4 V, whereas that of the transistor with Al electrodes was −1.8; this shift is attributed to the fact that Ti has a higher work function than Al. When Ti was used as the source and drain electrode material, the channel resistance and effective channel length were reduced owing to the penetration of metal atoms into the channel region from the edge of the source/drain electrodes.

In this paper, we propose the design optimization of underlapped Si1–xGex-source tunneling field-effect transistors (TFETs) with a gate-all-around structure. The band-to-band tunneling rates, tunneling barrier widths, I–V transfer characteristics, threshold voltages, on/off current ratios, and subthreshold swings (SSs) were analyzed by varying the Ge mole fraction of the Si1–xGex source using a commercial device simulator. In particular, a Si0.2Ge0.8-source TFET among our proposed TFETs exhibits an on/off current ratio of approximately 1013, and SS of 27.4 mV/dec.

In this study, we propose an integrate-and-fire (I&F) neuron circuit using a p-n-p-n diode that utilizes a latch-up phenomenon and investigate the I&F operation without external bias voltages using mixed-mode technology computer-aided design (TCAD) simulations. The neuron circuit composed of one p-n-p-n diode, three MOSFETs, and a capacitor operates with no external bias lines, and its I&F operation has an energy consumption of 0.59 fJ with an energy efficiency of 96.3% per spike. The presented neuron circuit is superior in terms of structural simplicity, number of external bias lines, and energy efficiency in comparison with that constructed with only MOSFETs. Moreover, the neuron circuit exhibits the features of controlling the firing frequency through the amplitude and time width of the synaptic pulse despite of the reduced number of the components and no external bias lines.

We propose a new design for covered source–channel tunnel field-effect transistors (CSC-TFETs) with trench gate structures. The I – V characteristics, on / off current ratio, subthreshold swing, and band-to-band tunneling rate are analyzed using a commercial device simulator. Our proposed CSC-TFETs exhibit an on / off current ratio of approximately 1010, an on -current of approximately 10−5 A/μm at room temperature, and a subthreshold swing of less than 40 mV/decade. In addition, the on -current of the CSC-TFETs is ∼233 times that of conventional TFETs, demonstrating that the switching characteristics are superior to those of other silicon-based TFETs. Moreover, a CSC-TFET inverter is characterized by SPICE calibration and provides a high frequency of approximately 1 GHz at a supply voltage of 1.0 V.

In this paper, we propose a novel static random access memory (SRAM) unit cell design and its array structure consisting of single-gated feedback field-effect transistors (FBFETs). To verify the SRAM characteristics, the basic memory operations and write disturbances of the unit cell are investigated through the mixed-mode technology computer-aided design simulations. The unit cell exhibits the superior SRAM characteristics including a write speed of 0.6 ns, a fast read-out speed of ~0.1 ns, and a retention time of 3600 s. Furthermore, the unit cell design exhibits advantages in density, with a small cell area of 8F2, and in the power consumption; the standby power consumption is 0.24 nW/bit for holding “1” and negligible for holding “0.” Moreover, our SRAM array shows reliable ${3} \times {3}$ array operations without any disturbances. This paper demonstrates the promising potential of the FBFET SRAM for high-performance, high-density, and low-power memory applications.

Black phosphorus (BP) has distinctive properties of tunable direct band gap as a semiconductor material, and both high carrier mobility and on/off switching performance for electronic devices, but has a significant drawback of material degradation in ambient atmosphere. Also, unlike graphene or MoS2, BP is only synthesized in bulk shapes limiting the fabrication of thin film-based devices. We demonstrated a contact printing process for BP field effect transistors (FET) with the steps of mechanical exfoliation of BP flakes and their randomized stamping in dry-transfer regime. The contact printing featured by fast, continuous and solvent-free process on the pre-patterned electrodes guarantees high process efficiency providing immunity against the chemical degradation of BP layers. With asymmetric I-V characteristics, the resultant BP-channelized FET shows the electrical properties of on/off current ratio, hole mobility, and subthreshold swing as > 102, ~ 130 cm2/Vs, and ~ 4.6 V/dec, respectively.

In this study, we examine the electrical characteristics of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) under bending strains by TCAD and SPICE simulations. Bending strains induce modifications of the localized density of states (DOS) in a-IGZO channel materials, which, in turn, cause changes in the electrical characteristics of the TFTs. The bending-strain-induced localized DOS, the above-threshold current, subthreshold current, and field-effect mobility are analyzed with the calibration of the current-versus-voltage curves of a reference device by TCAD simulation. Moreover, the device parameters that affect the device performance in SPICE simulation are calibrated to aid in SPICE modeling of the strained oxide TFTs.

In this study, we fabricate solid-state flexible micro-supercapacitors (MSCs) with reduced graphene oxide-carbon nanotube (rGO-CNT) composite electrodes and investigate the electrochemical characteristics by comparing with those of an MSC with rGO electrodes. Regarding the resistance-capacitance time constant and IR drop, the addition of CNTs into the rGO electrodes shows a significant effect owing to both the decrease in the resistance and the increase in the permeability of the electrolytes. Compared to the rGO MSCs, the rGO-CNT MSCs show an excellent areal capacitance of 2.6 mF/cm2, a smaller IR drop of 11 mV, a lower RC time constant of 6 ms, and faster charging/discharging rates with a high scan rate ability up to 100 V/s. The mechanical stability of the flexible rGO-CNT MSCs is verified by 1000 bending cycles. In addition, the electrochemical characteristics of the flexible rGO-CNT MSCs are maintained regardless of the MSC array type.

In this study, we fabricate the amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) on a stretchable substrate with a buffer stage and investigate the mechanical stability and electrical characteristics when the length of the substrate is stretched by 1.7 times. The buffer stage is responsible for the stiffness modulation of the stretchable substrate. The mobility, the threshold voltage and the on/off ratio of the stretchable a-IGZO TFT are measured to be 18.1 cm2/V·s, 1 V, and 3 × 107, respectively. Our simulation conducted by a three dimensional finite elements method reveals that the stiffness modulation reduces the stress experienced by the substrate in the stretched state by about one-tenth. In addition, the mechanical stability and electrical characteristics of the a-IGZO TFT are maintained even when the substrate is stretched by 1.7 times.

In this study, we propose a precise model of silicon tunneling field-effect transistors (TFETs) by modifying the Kane-Sze tunneling formula. In our model, a reference device is calibrated by utilizing TCAD and SPICE simulation. Electrical parameters extracted in our TCAD simulation are applied to a SPICE model not only for adopting the off-state current of a p-i-n diode under a reverse bias state but also for developing the threshold voltage and electric field equations. Furthermore, a basic complementary TFET inverter is simulated to demonstrate the capabilities of our proposed model.

In this paper, we investigate the performance of ring oscillators composed of gate-all-around (GAA) silicon nanowire (NW) field-effect transistors (FETs) with four different numbers of NW channels, for sub-10-nm logic applications. Our simulations reveal that ring oscillators with double, triple, and quadruple NW channels exhibit improvements of up to 50%, 85%, and 97%, respectively, in the oscillation frequencies (fosc), compared to a ring oscillator with a single NW channel, due to the large drive current, in spite of the increased intrinsic capacitance of a given device. Moreover, our work shows that the fosc improvement ratio of the ring oscillators becomes saturated with triple NW channels with additional load capacitances of 0.1 fF and 0.01 fF, which are similar to, or less than the intrinsic device capacitance (∼0.1 fF). Thus, our study provides an insight for determining the capacitive load and optimal number of NW channels, for device development and circuit design of GAA NW FETs.

Solution- p-type thin-film transistors, consisting of sol-gel-processed CuO films, were fabricated. The optoelectric properties of sol-gel-processed, CuO-based back gate thin-film transistors were investigated, and a detectivity of $1.38\times 10^{ {11}}$ (cm Hz $^{ {1/2}}~\text{W}^{-1})$ was achieved. This detectivity for sol-gel-processed CuO thin-film transistors is higher than that of the previously reported layered two-dimensional material systems and comparable to that of devices based on a one-dimensional nanowire system. Our results indicate that the sol-gel–processed, CuO-based photodetector system is a promising candidate for applications, such as near-infrared imaging devices, sensors, solar cells, and p-type inks for future printed electronics.

In this study, we investigate threshold voltage (VTH) variability of metal-oxide-semiconductor field-effect transistors induced by random dopant fluctuation (RDF). Our simulation work demonstrates not only the influence of the implantation parameters such as its dose, tilt angle, energy, and rotation angle on the RDF-induced VTH variability, but also the solution to reduce the effect of this variability. By adjusting the ion implantation parameters, the 3σ (VTH) is reduced from 43.8 mV to 28.9 mV. This 34% reduction is significant, considering that our technique is very cost effective and facilitates easy fabrication, increasing availability.

In this paper, we present the impact ionization and tunneling operations in a newly designed dopingless device. Our proposed device functions selectively—as either a p-channel impact-ionization MOSFET (p-IMOS) or an n-channel tunneling field-effect transistor (n-TFET)—according to the bias conditions. To realize the dopingless device, the charge-plasma effect is employed to induce n- or p-type regions without any doping process, by choosing an electrode metal with an appropriate work function. The band diagrams, I–V characteristics, subthreshold swings (SS), and carrier-concentration profiles of the device under the p-IMOS and n-TFET operation modes are analyzed in our study, using a commercial device simulator. The device yields an extremely low SS of 0.53 mV/dec under the p-IMOS operation mode. It also exhibits a low off-current of approximately 10−14 A/μm and a high ION/IOFF of approximately 108, under the n-TFET operation mode.

In this study, we examined mechanical strain-induced defect states in hydrogenated amorphous silicon (a-Si:H) channel layers of thin-film transistors (TFTs) bent with a curvature radius of 18 mm. When strain is applied to the TFTs, our devices feature strain-induced variations in threshold voltage (~ 1.47 V), subthreshold swing (~ 0.36 V/dec), and field-effect mobility (~ 0.031 cm2 V− 1 s− 1). The electrical characteristics of a-Si:H TFTs on bendable substrates under mechanical strain are explained by the variation in the density of states (DOS) of defects in the channel layers. Our simulation work on the DOS in the a-Si:H channel layers under mechanical strain reveals that the mechanical strain causes not only the deformation of the density of mid-gap defect states but also an increase in the band-tail states within the band gap.

In this study, we demonstrate the static random access memory (SRAM) characteristics generated by weak impact ionization in bendable field-effect transistors (FETs) with n+-p-n+ silicon nanowire (SiNW) channels. Our bendable SiNW FETs show not only superior switching characteristics such as an on/off current ratio of ~105 and steep subthreshold swing (~5 mV/dec) but also reliable SRAM characteristics. The SRAM characteristics originate from the positive feedback loops in the SiNW FETs generated by weak impact ionization. This paper describes in detail the operating mechanism of our device and demonstrates the potential of bendable SiNW FETs for future SRAM applications.

In this paper, we propose inverting logic-in-memory (LIM) cells comprising silicon nanowire feedback field-effect transistors with steep switching and holding characteristics. The timing diagrams of the proposed inverting LIM cells under dynamic and static conditions are investigated via mixed-mode technology computer-aided design simulation to verify the performance. The inverting LIM cells have an operating speed of the order of nanoseconds, an ultra-high voltage gain, and a longer retention time than that of conventional dynamic random access memory. The disturbance characteristics of half-selected cells within an inverting LIM array confirm the appropriate functioning of the random access memory array.

In this paper, we propose a novel construction of silicon nanowire (SiNW) negative-AND (NAND) logic gates on bendable plastic substrates and describe their electrical characteristics. The NAND logic gates with SiNW channels are capable of operating with a supply voltage as low as 0.8 V, with switching and standby power consumption of approximately 1.1 and 0.068 nW, respectively. Superior electrical characteristics of each SiNW transistor, including steep subthreshold slopes, high I on/off ratio, and symmetrical threshold voltages, are the major factors that enable nanowatt-range power operation of the logic gates. Moreover, the mechanical bendability of the logic gates indicates that they have good and stable fatigue properties.

In this study, we fabricate top-gate amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) with five split channels on a bendable plastic substrate and investigate the electrical characteristics as a function of bending curvature radius. Owing to the channel width splitting effect, our TFTs have outstanding characteristics including a high mobility of 71.8cm2/Vźs and an on/off ratio of 108. Our bending study reveals that the operation regions of our TFT are categorized into safe, transition, and definitive mechanical failure regions as the value of the bending curvature radius decreases. In the transition region, the threshold voltage is shifted from 1.0 to 2.1V, and the mobility is decreased from 71.8 to 25.9cm2/Vźs. The electrical failure of bendable TFTs results from microcracks induced by mechanical strain. Display Omitted We fabricate bendable a-IGZO TFTs with five-split channels on a plastic substrate.The channel width splitting effect leads to the outstanding characteristics of TFT.We investigate electrical properties of a-IGZO TFT as a function of bending radius.We categorize the operations of TFT into three regions with the bending strain.

In this paper, we demonstrate the low-power functionality of silicon nanowire (SiNW)-assembled inverters on bendable plastics. Our bendable inverters are capable of operating at supply voltages as low as 0.8 V with a switching (or standby) power consumption of ∼0.2 nW (or ∼6.6 pW). The low-power inverting operation with a voltage gain of ∼18 is attributable to the near-ideal characteristics of the component transistors that have selectively thinned SiNW channels and exhibit low, symmetrical threshold voltages of 0.40 and −0.39 V and low sub-threshold swing values of 81 and 65 mV/dec. Moreover, mechanical bendability reveals that the inverting operation has good, stable fatigue properties.

In this study, we fabricate transparent and bendable a-IGZO (amorphous indium gallium zinc oxide) TFTs (thin-film transistors) with a-IZO (amorphous indium zinc oxide) transparent electrodes on plastic substrates and investigate their electrical characteristics under bending states. Our a-IGZO TFTs show a high transmittance of 82% at a wavelength of 550 nm. And these TFTs have an ratio of , a field effect mobility of , and a subthreshold swing of 186 mV/dec. The good electrical characteristics are retained even after bending with a curvature radius of 18 mm corresponding to a strain of 0.5% owing to mechanical durability of the transparent electrodes used in this study.

In this study, we propose a simple way to improve thermal stability of solid-state supercapacitors (SCs) by adding carbon black (CB) into reduced graphene oxide (rGO) electrodes. The CB used as a heat-resistant additive contributes to stable operation of the rGO-CB SC even after 1000 charge/discharge cycles at 90 °C. In the case of the rGO SC without CB, it fails after the 166th cycles at 90 °C. Compared with the rGO SC, the rGO-CB SC exhibits the decrease in internal resistance from 42 to 18 Ω and the increase in specific capacitance from 115 to 160 F/g. Moreover, the rGO-CB SC shows a smaller variation in specific capacitance (12%) than that of rGO SC (30%) as the temperature increases from 30 to 90 °C. The observation reveals that the addition of CB being a heat-resistant additive helps improve performance of thermal stable SCs.

In this paper, we investigate the performance of inverters and ring oscillators composed of gate-all-around (GAA) silicon nanowire and nanosheet (NSH) field-effect transistors (FETs), compared with FinFETs, for sub-10nm logic technology applications. Our TCAD transient simulations reveal that ring oscillators with 3 stacked channels with NSH width, three times wider than the fin width, exhibit improvements of up to 22% in the oscillation frequencies. compared to a ring oscillator with FinFETs. Thus, our study provides an insight for device down-selection in the development of GAA FET technology.

The trap-assisted green electroluminescence (EL) efficiency of a light-emitting diode (LED) consisting of a ZnO nanowire (NW), a SiO2 layer, and a Si NW on a bendable substrate is enhanced by piezophototronic effect. The green EL originates from radiative recombination through deep-level defects such as interstitial zinc, interstitial oxygen, oxygen antisite, and zinc vacancy in the component ZnO NW. The efficiency of the trap-assisted green EL is enhanced by a piezophototronic factor of 2.79 under a strain of 0.006%. The piezoelectric field built up inside the component ZnO NW improves the recombination rate of the electron-hole pairs thereby enhancing the efficiency of the trap-assisted green EL.

In this study, we propose a novel combination of tunneling field-effect transistors (TFETs) with asymmetrically doped p+-i-n+ silicon nanowire (SiNW) channels on a bendable substrate. The combination of two n-channel SiNW-TFETs (NWTFETs) in parallel and two p-channel NWTFETs in series operates as a two-input NOR logic gate. The component NWTFETs with the n- and p-channels exhibit subthreshold swings (SSs) of 69 and 53 mV·dec−1, respectively, and the on/off current ratios are ~106. The NOR logic operation is sustainable and reproducible for up to 1,000 bending cycles with a narrow transition width of ~0.26 V. The mechanical bendability of the bendable NWTFETs shows that they are stable and have good fatigue properties. To the best of our knowledge, this is the first study on the electrical and mechanical characteristics of a bendable NOR logic gate composed of NWTFETs.

Display Omitted Si nanowires are fabricated by fully CMOS-compatible top-down route.Ring oscillator is fabricated on the polyethersulphone (PES) flexible substrate.We report a flexible ring oscillator which features 1-V operation.Ring oscillator generated a sinusoidal wave with a frequency of ~6.6MHz. In this study, we propose a flexible silicon nanowire (SiNW) low-power ring oscillator, which features 1-V operation. Our flexible ring oscillator is composed of three CMOS inverters with a gain of 70 at a supply voltage of 1V. p- and n-channel SiNW field-effect transistors (FETs) forming the component inverters exhibit on/off current ratios of 4.36×104 and 1.46×105, respectively. Our ring oscillator generates a sinusoidal wave with a frequency of ~6.6MHz. The frequency and waveform are undistorted under upwardly bent and downwardly bent strain conditions of 0.7%. The good mechanical bendability of the flexible ring oscillator indicates high stability and good fatigue properties.

Dual-functional devices based on gated p-i-n diodes are proposed in this simulation study. The dual-functional devices function not only as n-channel tunneling field-effect transistors (n-TFETs) but also as p-channel impact-ionization FETs (p-IFETs), depending on the bias conditions. In this study, the I–V characteristics, subthreshold swing ( SS ), ON/OFF current ratio ( $I_{{\rm on}}/I_{{\rm off}}$ ), and band diagram are analyzed using a device simulator (Silvaco Atlas), and the features of the n-TFETs and the p-IFETs are extracted from the simulated data. The n-TFETs exhibit high $I_{{\rm on}}/I_{{\rm off}} $ of ∼1011 and a sub-60-mV/dec SS , and the p-IFETs yield extremely low SS of as small as 8.57 mV/dec. Our approach is one of the useful methods to design multifunctional electronics for lowering the power consumption.

In this study, we demonstrate the simulated subthreshold swing ( SS ) of silicon nanowire tunneling field-effect transistors (NWTFETs) by varying both the channel diameter from 10 nm to 40 nm and the gate coverage ratio from 30% to 100%. Our simulation work reveals that both a decrease in the channel diameter and an increase in the gate coverage ratio contribute to a reduction in the SS . Additionally, our work shows that the magnitude of the on-current depends linearly on the gate coverage ratio and that the drain current increases with a decrease in the channel diameter. Thus, an NWTFET with a channel diameter of 10 nm and a gate coverage ratio of 100% exhibits superior electrical characteristics over other silicon NWTFETs in that the NWTFET shows a point SS of 22.7 mV/dec, an average SS of 56.3 mV/dec, an on/off current ratio of ∼10 13 , and an on-current of ∼10 −5 A/μm.

Graphene/carbon nanotube (CNT) junction barrier height was investigated using all-carbon field-effect transistor structure with graphene and single-walled CNT (SWCNT) network as source (S)/drain (D)/gate electrodes and as channel, respectively. SWCNT network channel was formed by dielectricphoresis process at the prepatterned graphene S/D electrodes. By analyzing the measured current–voltage characteristics by the diode circuit model, the Schottky barrier height at the graphene and CNT junction was found to be approximately 0.5 eV.

In this paper, we demonstrate the vertical stacking of ZnO nanowire (NW) field-effect transistors (FETs), a ZnO NW-based nanofloating gate memory (NFGM) device, and a ZnO NW-based inverter on a flexible plastic substrate. For the vertical stacking, four ZnO NW devices are sequentially constructed on each of four layers, and these devices are isolated from each other using Al2O3 material. Each of the stacked ZnO NW devices exhibits the good electrical characteristics with n-type depletion modes under both the flat and bent states. Moreover, the switching, memory, and inverting characteristics of the stacked ZnO NW devices are examined.

In this work, a single ZnO nanowire field-effect transistor (NWFET) with discrete-trap storage nodes of Pt nanocrystals (NCs) embedded within Al2O3, a high-κ tunneling/control dielectric material, was successfully fabricated on a flexible plastic substrate for a non-volatile memory application. The ZnO NWFET with embedded Pt NCs exhibits a clear hysteresis loop with a threshold voltage shift of 4.16 V under the ±15 V gate–source voltage sweep ranges, implying that the charging and discharging phenomena occur during the program/erase operations. The ZnO NWFET achieves a reasonable value of approximately 105 for the on/off current ratio for read-out of storage data. Furthermore, memory features, such as programming efficiency and on-cell current, are compared between the flat and convexly bent states in order to investigate the feasibility of flexible plastic devices as transistors.

In this study, large area mono-, bi-, and multi-layer graphenes (MLG) were synthesized using low pressure chemical vapor deposition (LPCVD) process and co-planar waveguides (CPW) with graphenes being fabricated using conventional photolithography. The intrinsic room temperature radio frequency (RF) characteristics were measured via direct contact to the graphene surface with a probe–tip in the range of 0.1 GHz to 40 GHz without using metal electrodes. The device characteristics were also evaluated by physics-based RLC equivalent circuit simulation. The proposed equivalent circuit model reproduced all of the measured characteristics within 3% of RMSE and we numerically extracted the set of component values which minimize the error between the measured data and the simulation results over the measured regime. Our findings demonstrate that MLG is an effective candidate in RF interconnect device applications. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

In this study, we demonstrate the abruptly steep-switching characteristics of a feedback field-effect transistor (FBFET) with a channel consisting of a p(+)-i-n(+) Si nanowire (NW) and charge spacers of discrete nanocrystals on a plastic substrate. The NW FBFET shows superior switching characteristics such as an on/off current ratio of ∼10(5) and an average subthreshold swing (SS) of 30.2 mV/dec at room temperature. Moreover, the average SS and threshold voltage values can be adjusted by programming. These sharp switching characteristics originate from a positive feedback loop generated by potential barriers in the intrinsic channel area. This paper describes in detail the switching mechanism of our device.

In this paper, we report the construction of avalanche photodetectors (APDs) consisting of p+-type/intrinsic/n+-type (p+-i -n+) Si nanowires (NWs) on a flexible plastic substrate and investigate the photomultiplication characteristics of the APDs with different intrinsic lengths. The maximum avalanche gain and responsivity of the APDs excited by the 633 nm wavelength light are estimated to be 5.9×104 and 1.4×10–3 A/W, respectively, for an intrinsic length of 0.5 μm. The maximum avalanche gain is associated with an improvement of the photomultiplication properties and results in the efficient generation of photogenerated charge carriers in the intrinsic region of the Si NWs. Furthermore, the breakdown phenomena in our APDs in the flat and upwardly bent states are investigated. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

High-performance amorphous SiZnSnO thin-film transistors (a-SZTO TFTs) were fabricated using radio-frequency (RF) magnetron sputtering. The noise spectral density of a-SZTO TFTs measured by using the drain current has been reported, and it was found that is possible to apply the conventional 1/fa theory to the low-frequency noise (LFN) of the a-SZTO TFTs. The LFN characteristics of a-SZTO TFTs can be clearly identified by the correlated number fluctuation-mobility fluctuation model. Based on the noise properties, the interfacial trap density (NT) was decreased from 2.32 × 1019 to 1.33 × 1019 cm−3 eV−1 as increasing Si ratio in a-SZTO TFTs. The electrical characteristics and LFN properties of a-SZTO TFTs varied strongly depending on the Si ratio, mainly because the Si atom can act as an oxygen vacancy suppressor.

In this study, we present an optically tunable feedback field-effect transistor (FBFET) with two independent gates and a p+-i-n+ silicon nanowire. Because of the feedback operation, the FBFET features extremely steep switching characteristics with subthreshold swings alt; 4 mV/dec, and it can be reconfigured as a p- or n-type transistor by controlling the gate-voltage biases. When the FBFET is exposed to a He?Ne laser beam (? = 633 nm), photogenerated carriers accumulate in the potential wells and reduce the potential-barrier height. The optically tunable feedback operation is attributed to this lowering of the potential barrier caused by the light. The triggering voltages can be modulated according to illumination, even when feedback is being provided. This optically tunable transistor with excellent switching characteristics opens up possibilities for application in future optoelectronic devices.

An explicit surface potential calculation method of gate-all-around MOSFET (GAAMOSFET) devices which takes into account both interface trap charge and varying doping levels is presented. The results of the method are extensively verified by numerical simulation. Results from the model are used to find qualitative and quantitative effect of interface trap charge on subthreshold slope (SS) of GAAMOSFET devices. Further, design constraints of GAAMOSFET devices with emphasis on the effect of interface trap charge on device SS performance are investigated.

We report the construction and characterization of a representative vertical inverter with a nanoparticle (NP)-based p-channel thin-film transistor (TFT) and a NP-based n-channel TFT on a flexible substrate. The vertical inverter consists of a p-type HgTe NP-based TFT on the first-stair layer and an n-type HgSe NP-based TFT on the second-stair layer. In the vertical inverter, an isolation layer made of polyvinyl alcohol prevents the cross talk between these TFTs. The vertical inverter exhibits the typical inverter characteristics with a gain of 4, and the reproducible operation was obtained in the upward and downward bending states, as well as in the flat state. Moreover, the inverter characteristics were maintained even after 1000 bending cycles with 0.7% strain.