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Similar to other power semiconductors, gallium nitride enhancement-mode high-electron-mobility transistors (GaN E-HEMTs) require short-circuit protection (SCP) or overcurrent protection (OCP) in practical applications. However, the fast-switching characteristic of GaN introduces the challenge to the protection. For SCP, the traditional methods are either too slow or not practical for GaN. Therefore, an alternative SCP solution, which is fast and easy to implement, is much desired. For high power density applications, it is also popular to integrate OCP into the gate driver. Therefore, a fast protection circuit that can be used for either SCP or OCP is desirable. In this article, an ultrafast discrete circuit-based protection circuit is proposed for GaN HEMTs. It includes a first soft turn- off stage and a second hard turn- off stage. The soft turn- off stage effectively limits the voltage spike over the device. Following the soft turn- off stage, the hard turn- off stage will cut off the pulsewidth modulation signal immediately completely. A dual-gate implementation approach is further proposed for devices with two gate pads. The method has been verified by both SPICE simulation and hardware implementations for both SCP and OCP. The experimental results show that the total propagation delay time for SCP is only 125 ns while the normal switching performance is not affected.

In this study, a simple memristor circuit using only one Voltage Differencing Current Conveyor (VDCC), two PMOS transistors and one grounded capacitor, is designed. The presented memristor exhibits electronically controllable characteristics, which are superior to its counterparts. Both the memductance value and the operating frequency can be electronically tuned through voltage sources. The proposed memristor, which occupies 42.2 µm × 27.5 µm area excluding the area of the capacitor, is laid by using Cadence Environment using TSMC 0.18 µm process parameters. In addition, the proposed memristor is implemented by using discrete circuit elements on the breadboard and detailed analyses are given by changing the values of the discrete circuit elements. All results are compatible with the previous studies.

The memcapacitor is one of the new memory circuit elements although it is not found on the market as a discrete circuit element. In this study, two simple memcapacitor emulators were developed using active circuit elements. These proposed circuits are both electronically controllable. The relationship between charge and flux depending on different frequencies was obtained for both presented memcapacitor circuits. To demonstrate the experimental response of the circuit, discrete circuit elements were used to build the first proposed circuit on the breadboard. All experimental results showed good agreement with the theoretical analyses.

Voltage amplification is an important element of the energy harvesting process to provide an enhanced voltage and run various digital circuits at low power. At RF frequencies, the discrete circuit arrangement using high frequency diode HSMS 2850 and capacitors have been used here to provide the voltage amplification with high power efficiency. The paper describes a mechanism of the Dickson circuit arrangement with its various parameters. The power efficiency is obtained and compared with multiple stages of the Dickson configuration for the input power, frequency of operation and its load using keysight based ADS tool. Finally a neural network has been designed using a Matlab script and the trained neural network has been applied to get the efficiency result. The result shows that with an increase in the multiplier stage of the Dickson circuit, there is a significant increase in its power efficiency. In addition the neural network implementation shows that the circuit parameters can be obtained using a well-trained neural network script.

The evolution of resistive switching device (memristor) technology during the last ten years has shown the great potential of such emerging nanoelectronic devices in several potential applications, ranging from memory to computing and sensing. As memristor technology is continuously maturing, more devices become commercially available and thus accessible to investigators working on relevant research topics, as well as to university teaching labs and academics who wish to incorporate memristor-related experiments in their classrooms. However, experimental work on circuits with memristors requires particular caution and supervision, given that such devices are both highly sensitive (i.e., can easily burn out) and still quite expensive compared to other discrete circuit components. In this context, the development of integrated instrumentation solutions that provide a safe way to experimental work with memristors is becoming increasingly relevant, and some such tools have already reached the market. In this direction, we present some early results from our experience on the design and development of an instrumentation printed circuit board (PCB), designed to provide an ad hoc low-cost solution for measurements on memristors. The driving circuitry on the PCB is interfaced through a microcontroller-based system, providing easy programming and acquisition for a variety of measurements.

Paper describes the research on the output resistance of the nanosecond pulse generator built on a Step Recovery Diode. Such generators are used as sources of short (tenths of a nanosecond) pulses. The latter are the basis for: measuring instruments, impact excitation of ultra-wideband antennas of radar sensors, radar of underground sounding and other purposes. To enable a comprehensive analysis of elements the system of differential algebraic equations is solved. The Equations are written for Kirchhoff's laws, describing the “behavior” of currents and voltages of discrete circuit elements, and the parasitic inductors and capacitors also. This is caused by strong influence of parasitic components on transients in the circuit, operating in the time range of less than a nanosecond, which is equivalent to the gigahertz frequencies and higher. The obtained solutions made it possible to reveal the influence of the nominal values of the generator circuit elements on its output resistance. Adjusting the output resistance of the generator to a value close to the characteristic resistance of the line, through which the pulses of the generator are transmitted to the load, maximize the transmission of power to the load and eliminate masking of the useful signal by pulses of re-reflections in the line.

In this paper we have designed a grounded memcapacitor emulator which is a part of memristive system providing a nonlinear relationship between Charge and Voltage. The Floating Current Source (FCS) possesses a low power consumption feature, has been utilized for the memcapacitor emulation. In this study, a memcapacitor emulator is designed utilizing discrete circuit elements. The proposed emulator circuit exhibits a simple design consisting of MOSFETs and capacitors. The emulator performance is verified theoretically, and computer simulations and results are discussed here.

This article is devoted to the development of analytically described self-oscillation stability research technique. The case when the linear part of the system contains transfer function with a zero pole is considered. Typically the transfer function study, where the numerator degree is two orders of magnitude less than the denominator degree is creates no problems. However, the presence of a zero pole makes the case special and requires investigation.A comparative evaluation of the results of self-oscillation analytical calculation and stability analysis is given, by means of technique developed for symmetric self-oscillations with half-period repetitions and asymmetric ones with period repetitions.The presented technique is a significantly new scientific step in the development of methods for calculating non-linear systems. It also allows us to evaluate the accuracy of approximate calculation methods, which is important for precision systems. The technique is relatively easy to implement. It allows to find a solution as well as for the cases having been unanalyzable so far.

In this paper, memristor emulator circuit consisting of only seven MOS transistors and one grounded capacitor is presented. Memristors exhibit nonlinear voltage-current relationship and many previous emulator circuits have multiplier circuit to provide the nonlinear characteristic of the memristor. But there is no any multiplier circuit block in the proposed circuit so the proposed memristor circuit occupies low chip area. The memristor circuit is laid by using Cadence Environment with TSMC 0.18 µm process parameters and its layout dimensions are only 12 µm × 38 µm excluding the area of the capacitor. The post-layout simulation results for memristor are given to demonstrate the performance of the presented memristor emulator in different operating frequencies, process corner, and radical temperature changes. All post-layout simulations agree well with theoretical analyses. Besides the VLSI implementation of the memristor, the proposed circuit is built on the breadboard using discrete circuit elements.

Made available in DSpace on 2019-10-06T16:54:29Z (GMT). No. of bitstreams: 0 Previous issue date: 2018-12-15 This work presents an unprecedented technique capable of representing grounding grids directly in the time domain using an association of passive and discrete circuit elements (RLC circuits: resistors, inductors and capacitors). It is based on the frequency response of RLC circuits and ensures that all elements will be positive (physically implementable), solving situations that other techniques, such as vector fitting, generally presented in the literature are not able to solve using only passive circuits (feasible). The proposed technique is applied from the harmonic impedance previously provided, and therefore this impedance can be obtained using any model. It is accurate; it presents excellent results and was validated by comparing the harmonic admittance and transient voltage curves to those obtained with the hybrid electromagnetic model. The advantage of this technique is that it allows that several components in power systems, such as grounding systems and transmission towers, to be represented by a feasible circuit. Once this circuit is implemented in the laboratory, analysis and comparisons with conventional software (e.g. ATP) can be made and accurate transient electromagnetic responses can be obtained. Campus Votuporanga Federal Institute of São Paulo - IFSP, Av. Jerônimo Figueira da Costa - 3014 Electrical Engineering Department São Paulo State University - UNESP, Av. Brasil Sul - 56 Electrical Engineering Department São Paulo State University - UNESP, Av. Brasil Sul - 56

The DC electrical behavior of n-type 4H-SiC resistors used for realizing 500 °C durable integrated circuits (ICs) is studied as a function of substrate bias and temperature. Improved fidelity electrical simulation is described using SPICE NMOS model to simulate resistor substrate body bias effect that is absent from the SPICE semiconductor resistor model.

This paper demonstrates a study of a switch-bridge-based readout circuit for differential capacitance measurement in MEMS resonators. The proposed switch-bridge circuit is improved upon a diode-bridge circuit, which is simple, highly sensitive, and environmentally robust. However, the diode-bridge circuit suffers an output limitation due to the requirement of reverse-bias for diodes. The switch-bridge circuit keeps the advantages of the diode-bridge circuit but eliminates its limitation by replacing diodes with switches. As a result, the sensitivity of the switch-bridge circuit can be further improved by increasing the reference voltage. The presented behaviors and characteristics of the switch-bridge circuit are also suitable for the diode-bridge circuit, whose detailed theoretical analyses have not been reported yet. Then, we introduce an error model to investigate the impacts of nonideal switches in practical applications. In addition, the noise feature is discussed by using a power spectral density model. Experimental results show that the switch-bridge-based readout circuit, when applied to a capacitive MEMS gyroscope, achieves a gain of 7.1 V/pF, or equivalently 1.96 V/ $\mu {\mathrm{ m}}$ , and a noise density of 0.077 aF/sqrt(Hz) between 20 Hz to 50 kHz.

Memcapacitors are become one of the research interest after the realization of memristors. Many researchers focused on the designing memcapacitor emulator because of some fabrication difficulties of this new element. In this paper, Voltage Differencing Current Conveyor (VDCC) based memcapacitor emulator is developed. This emulator is composed of two VDCCs and can be electronically controllable. To show the operation performance of the proposed circuit, some analyses and memcapacitor based associative learning circuit are given. TSMC 0.18 µm process parameters are used to simulate the memcapacitor. The circuit is also implemented on breadboard using discrete circuit elements. Both theoretical and simulation results are good agreement when compared previous studies.

Thin-film transistors (TFT) in hydrogenated amorphoussilicon, amorphousmetal oxide, andsmallmolecule and polymer organic semiconductors would all hold promise as potential device candidates to large area flexible electronics applications. A universal compact dc model was developed with a proper balance between the physical and mathematical approaches for these thin-film transistors (TFTs). It can capture the common key parameters used for device performance benchmarking of the different TFTs while being applicable to a wide range of TFT technologies in different materials and device structures. Based on this model, a user-friendly tool was developed to provide an interactive way for convenient parameter extraction. The model is continuous from the off-state and subthreshold regimes to the above-threshold regime, avoiding the convergence problems when being used in SPICE circuit simulations. Finally, for verification, it was implemented into a SPICE circuit simulator using Verilog-A to simulate a TFT circuit examplewith the simulated results agreeing verywell with the experimental measurements.

Short-circuit detection is a fundamental function of most inverters. In this paper, two new fast and easily implementable short-circuit detection approaches are presented. The first one offers a significantly accelerated desaturation detection. The second one allows a full inverter to be protected by only one short-circuit detection circuit. Both approaches are verified by simulations and hardware tests.

This paper presents a high-temperature (HT) gate drive and protection circuit for Silicon-Carbide (SiC) power mosfets entirely built from commercial off-the-shelf HT discrete components. To estimate cost reduction, a brief comparison was made between the proposed circuit and a commercial circuit using silicon-on-insulator integrated circuits. To evaluate performance, power tests were conducted up to 180°C in a thermal chamber. Eventually, the proposed circuit achieved a 90% cost reduction, and all functions were validated by experiments at 180°C. This demonstrated that the proposed circuit is a cost-effective solution for contemporary HT applications.

In this work, a new compact CMOS potentiostat circuit for electrochemical sensors is proposed. Integrated Potentiostats in CMOS technology are usually found in the literature designed with operational amplifiers performing both the electrochemical sensor bias and signal readout. In order to present alternative circuitry, a new potentiostat topology composed of a two-stage operational amplifier and a current conveyor circuit is proposed. The current conveyor is employed to perform the bias signal readout of an electrochemical cell with three electrodes. Simulations and experimental results of a discrete circuit version show that the proposed potentiostat topology yields results compliant with those of classical topologies presented in the literature.

Bipolar junction transistors (BJTs) have been widely studied and used in nanosecond high-voltage pulse generators due to the advantages of fast switching speed and high repetitive frequency. Usually the Marx-type circuit is used to raise the peak value of output pulses. In this paper, a traditional BJT-Marx circuit using charging resistors is analyzed theoretically and experimentally. Based on the results, the structure of a circuit is changed to decrease the isolation voltage across the resistors, and diodes are used to replace charging resistors to block capacitors discharging to resistors. Experimental results showed that the three Marx generators proposed in this paper output pulses with higher voltage amplitude, and the last improved circuit outputs pulses with faster fall times at a higher efficiency.

In this paper, we propose two emulator circuits. Firstly, we present a novel memristor emulator based on operational transconductance amplifier (OTA) which is different from classical TiO2 memristor. This memristor emulator has a threshold switching mechanism. Secondly, we create a novel neuron circuit using proposed memristor, which is capable of generating spiking and bursting firing behaviors, with a biologically plausible spike shapes. The behavior of this neuron circuit can be adjusted by changing only one external biasing voltage. This neuron circuit mimics the behavior of cortical neurons, such as regular spiking (RS), intrinsic bursting (IB), chattering (CH) and fast spiking (FS). Proposed emulator circuits are compatible with VLSI systems and they can also be implemented by using discrete circuit components for different applications.

This article describes heat dissipation challenges in 3-D ICs; using two case studies, it also presents insights and design guidelines for 3-D thermal management.

The need for dependable digital circuitry with the capability to operate reliably in high-temperature environments has been increasing drastically in applications such as automobile, aerospace, oil exploration, and power electronics. However, wide temperature swings significantly alter the threshold voltage of individual transistors, which adversely affects circuit timing in traditional synchronous designs. Such timing changes may in turn violates the setup and hold times of the clocked components, leading to potential circuit failure. This paper presents a complex digital integrated circuit design methodology using both synchronous and asynchronous logic for comparison in a young silicon carbide (SiC) design process developed by Raytheon UK. Seventeen circuits were designed, fabricated, and tested with results showing correct operation at temperatures at and above the target temperature of 300 °C.

Through silicon via (TSV) is the enabling technology for 3-D integrated circuit (IC) realization. To develop manufacturing tests for 3-D ICs, TSV has to be accurately modeled. Analytical methods are commonly used to develop circuit models for TSVs. These models are often difficult to develop and require some assumptions to simplify the problem. This paper presents a new method utilizing computer-aided design tools to extract circuit models for prebond and postbond TSVs. It is shown how the effects of common TSV parametric and catastrophic faults such as pinholes, voids, and open circuits affect TSV circuit models through 3-D full-wave simulations. It is also shown that the substrate conductivity has a considerable effect on the TSV fault characterization. The extracted models indicate that even a relatively large void does not alter the TSV characteristic parameters and thus voids remain largely undetected with conventional test solutions. An on-chip circuit, utilizing a delay-locked loop is presented as a test solution to detect TSV parametric faults.

Ability to supply more transistors per chip is outpacing improvements in cooling and power delivery. The result is operation that selectively powers on or off subsets of transistors. This paper suggests innovate ways to take advantage of the consequent “dark” silicon to meet a pair of additional emerging challenges—reliability and tolerance of variability.

Evaluation of novel devices in the context of circuits is crucial to identifying and maximizing their value. We propose a new framework, Pareto optimization-based circuit-level evaluator for emerging device (PROCEED), that uses comprehensive performance, power, and area metrics for accurate device-circuit coevaluation through optimization of digital circuit benchmarks. The PROCEED assesses technology suitability over a wide operating region (megahertz to gigahertz) by leveraging available circuit knobs (threshold voltage assignment, power management, sizing, and so on). It improves the benchmark accuracy by $3\times $ to $115\times $ compared with the existing methods while offering orders of magnitude improvements in runtime over full physical design implementation flows. To illustrate the PROCEED's capabilities, we deploy it to assess emerging technologies, including novel tunneling field-effect transistors, compared with conventional silicon CMOS. As a further illustration, we extend PROCEED to evaluate future heterogeneous integration of varied devices onto the same silicon substrate.

Beyond the 22-nm technology node, interconnect parasitics are increasingly contributing to the degradation of circuit performance. Thus, the focus is on optimizing interconnect parasitics in order to achieve optimum performance. The increased total device capacitance and the reduced device resistance of multigate transistors amplify the importance of wire resistance in circuit delay. In this paper, the impact of interconnect resistance on the circuit performance is weighed against interconnect capacitance, and less aggressive wire width and thickness scaling are proposed. This analysis is carried out based on the results from fully timing-closed, GDSII-level layout of circuit blocks, for the 11- and 7-nm technology nodes. The sensitivity of circuit power dissipation and signal noise to interconnect dimensions is assessed in detail. This approach compromises wire capacitance and gradually renders it important in circuit delay. The circuit performance enhancement by air-gap (AG) interconnect technology is studied with the traditional BEOL scaling versus the proposed wire sizing. It is found that using the latter wire sizing approach with air-gap interconnects is more beneficial to circuit performance.

This study presents a physical-based RF equivalent circuit model for CMOS transistors. To increase the model accuracy and extend the effective frequency band, the interconnection effects between the input–output pad and the gate–drain of the transistor are described by using a second-order distributed parameter transmission line equivalent circuit network. Both the extrinsic and intrinsic parameters in the model are extracted from the multibias scattering parameters. Based on the proposed model, the S-parameters are calculated and compared with the experimental results. The comparison shows that using second-order distributed parameter transmission line model can improve the phase accuracy of the model remarkably. The proposed model achieves a high accuracy up to 220 GHz.

In this paper, we have presented a Dual-Output Operational Transconductance Amplifier (DO-OTA) and Differential Voltage Current Conveyor (DVCC)-based fully floating emulator which enables the memristor current to flow in both directions when used with other circuit elements. The proposed memristor consists of only one DO-OTA, one DVCC, one grounded capacitor that is attractive for an integrated circuit, and two PMOS transistors operating as an electronic resistor. The proposed fully floating memristor emulator includes two very important features: (1) the fixed and variable memductance parts of the circuit are electronically adjustable, and (2) both incremental and decremental circuit behaviors can be obtained without altering the circuit topology. The circuit was laid using the Cadence Spectre Analog Environment with TSMC 0.18 µm process parameters and occupied a layout area of only 119 µm × 90 µm. The post-layout simulation results for the memristor circuit were obtained for different operating frequencies and all simulations were fully compatible with the experimental memristor behaviors. Finally, the memristor circuit was built on a breadboard using discrete circuit elements, and all experimental results were also compatible with the expected memristor characteristics.

Gallium Nitride enhancement-mode high electron mobility transistors (GaN E-HEMTs) are being designed into power electronic systems due to the fast switching capability. The GaN-based converters obtain higher efficiency, smaller size, and lower cost from the system point of view. On the other hand, the fast-switching characteristic of GaN also introduces the challenge of the short-circuit protection (SCP) and over-current protection (OCP). The traditional SCP/OCP methods are either too slow or not practical to the GaN device. Therefore, an alternative SCP/OCP solution which is fast and easy to implement is much desired for GaN HEMT. In this paper, an ultrafast discrete circuit of SCP for GaN HEMTs is proposed. The protection method includes two stages. The first-stage is soft turn-off, and the second-stage is hard turn-off. The soft turn-off can reduce the gate voltage gradually and thus limit the voltage spike on the DC-link. The method has been verified by both SPICE simulation and hardware implementation. The implementation results show that the propagation delay time for first-stage and second-stage are 85 ns and 125 ns, respectively. As a result, the proposed circuit is able to protect GaN HEMTs for short-circuit scenario under different DC-link voltages.

This paper presents an implementation of Threshold Logic Units (TLU), the special case of an Artificial Neural Network (ANN), using discrete circuit elements like memristors as synapses and CMOS circuits as a neuron. Simple threshold logic gates have been developed using a single layer network to establish a base upon which more complex problems can be implemented. The XOR problem, benchmark for a simple multilayer neural network circuit, has also been simulated in this paper as an example of multiple layer networks. Once the circuit is developed, the memristors are trained to their weights. The logical output of the neuron is checked whether the circuits are working or not. Successful demonstrations and simulation of the basic logic gates have been shown which can contribute to the development of using the memristor-based neural network.

The study proposed electro-optical measurement and process inspection for integrated-gate-driver circuit on thin-film-transistor array panel. It is a trend on the developing with application of integrated gate driver circuit in the narrow frame design and reduction of driver integrated circuit chips in thin-film-transistor array backplane. Over the past, it cannot detect that contain integrated-gate-driver circuit on thin-film-transistor array panel, especially in process defects of the integrated-gate-driver circuit. The paper proposed a process inspection for the defects in integrated-gate-driver circuit on the thin-film-transistor array panel by the voltage imaging technique and reported good performance.

This paper presents a novel and simple integrated gate driver circuit composed of only four thin-film transistors (TFTs) and three capacitors for slim-border and high-resolution applications. The input TFT has multi-functions to reduce the components of the circuit and its driving capability is enhanced to improve the rising time of the output waveform, so the size of the input TFT can be decreased. Moreover, the large-size pullup TFT is also used to discharge the row line for decreasing the falling time of the output waveform, so that an additional largesize pull-down TFT can be eliminated for further diminishing the circuit area. Importantly, an inverse-coupling method is introduced to suppress the noise of the row line, which can also lessen the number of TFTs and simplify the circuit structure.

A novel CMOS interface circuit with high resolution is designed and realized to achieve the integration of interface circuit for liquid suspended rotor micro-gyroscope. The detecting circuit adopts continuous-time current sensing circuit for capacitance measurement. The equivalent output noise power spectral density of phase-sensitive demodulation is 120 nV/Hz1/2. The whole circuitry is realized with 0.5 μm 2P2M CMOS process and its testing results show the circuit has a relative capacitance resolution of 1×10-8, in which the power supply is 18 V and the power consumption is 30 mW. The area of the chip is merely 18.5 mm2.

This paper presents a method for deriving circuit model stamp equations from the characteristic equations of multiterminal devices. The method is applied to the derivation of stamp equations of carbon nanotube and graphene nano-ribbon field-effect transistors (FETs) for use in general-purpose circuit simulators. We first review existing methods of modeling FETs for circuit simulation and point out some of the weaknesses in these models. We then explain how to derive model equation stamps directly from the device physical characteristic equations without the need of eliminating internal device variables and without having to construct equivalent circuits consisting of interconnections of two-terminal resistors, controlled sources, and two-terminal capacitors.

To improve battery cell balancing speed, a novel switched capacitor (SC) circuit combining the conventional SC circuit and the optimized SC circuit is proposed in this paper. It has the advantage that the balancing speed is independent of number increase as well as initial voltage variation of battery cells. The equivalent model of the proposed circuit is developed and analyzed in this paper. Compared with the optimized SC circuit, the balancing speed of the proposed circuit is doubled. Simulation comparisons with the conventional SC circuit and the optimized SC circuit under different numbers and initial voltages of battery cells are carried out in PSIM environment. Simulation results show 82% and 50% decrement in the balancing time averagely compared with the conventional SC circuit and the optimized SC circuit, respectively.

This paper presents a new LC resonant circuit using operational amplifier (Op-amp) for power supply of adiabatic logic. The concept of the proposed LC resonant circuit is the same as our previously proposed circuit in 2015 but the feature of the proposed circuit is that, the peak controller that has lower power consumption is composed of Op-amp based comparator and LPF. From the SPICE simulation results with 0.18 μm CMOS process, the power consumption of the proposed circuit is 22.6 μW, which is 36% less compared with the conventional one.

This paper presents a novel startup circuit that provides a startup operation for bias circuits and reference circuits. The proposed circuit employs delay buffer and series transistors to automatically turn off the startup circuit after the bias circuit has started. Thus, the proposed startup circuit consumes no power during the normal operation of the reference circuit and is useful for low-power circuits. The proposed circuit has been designed with a standard TSMC 0.18 µm 1P6M CMOS technology. Simulation result shows that a short startup time 7.6 ns can be achieved by controlling the proposed delay buffer.

Self powered energy management circuits make energy harvesting converters more efficient and more reliable. This paper presents an improvement of a self-powered parallel synchronized switch harvesting on inductor (P-SSHI) circuit for piezoelectric transducers. Two different switching techniques are evaluated, which are switching based on two MOSFETs controlled by two operational amplifiers and switching based on bipolar transistors. Simulation results show that the circuit using the switch based on bipolar transistors delivers a 19.2 times higher power comparing to the other switching technique. Optimization of this result is proposed by reducing losses in the circuit using less energy consuming components which increases the power output by more than 300% in comparison to formerly proposed solutions. The optimized circuit is designed and tested using a commercially available piezoelectric converter with and without a proof mass. Experimental results are compared to simulations made using the same excitation sources. A good agreement is found between the course of both simulation and experimental results.

Memristor has been proposed as the fourth missing fundamental circuit element in 1971. This new circuit element has a charge controlled resistance, saturation mechanism and zero-crossing hysteresis loop which cannot be mimicked by previously known circuit elements. It is a promising candidate for both digital and analog electric circuit applications. In this work, a memristor based timer circuit is proposed. Concept of the circuit is presented and its analysis is done. Simulation of the timer is done using the linear drift model of the TiO2 memristor and the result is compared to the analytical calculations.

This paper presents a new architecture for generating a multitude of circuit functions. The proposed computational structure will be able to amplify, multiply or square signals and, additionally, to replace a classical resistor with a both positive or negative resistance. As a consequence of using a multifunctional circuit, in order to realize four circuit function, the equivalent complexity for each implemented function can be strongly reduced. The newly proposed low-power low-voltage circuit has a minimal supply voltage of and its power consumption is between and .

A simple square-rooting circuit based on available operational amplifiers (op-amps) and available CMOS transistor arrays (CD4007) is proposed in this paper. This circuit has simple structure. It consists of two NMOS transistors and three op-amps. The output voltage of circuit can be either positive or negative by setting gain which can be easily adjusted by varying the resistors. Experimental results by using CD 4007 and μa741 are given to verify the operation.

To compare image quality and low-contrast detectability of an integrated circuit (IC) detector in abdominal CT of obese patients with conventional detector technology at low tube voltages. A liver phantom with 45 lesions was placed in a water container to mimic an obese patient and examined on two different CT systems at 80, 100 and 120 kVp. The systems were equipped with either the IC or conventional detector. Image noise was measured, and the contrast-to-noise-ratio (CNR) was calculated. Low-contrast detectability was assessed independently by three radiologists. Radiation dose was estimated by the volume CT dose index (CTDIvol). The image noise was significantly lower, and the CNR was significantly higher with the IC detector at 80, 100 and 120 kVp, respectively (P = 0.023). The IC detector resulted in an increased lesion detection rate at 80 kVp (38.1 % vs. 17.2 %) and 100 kVp (57.0 % vs. 41.0 %). There was no difference in the detection rate between the IC detector at 100 kVp and the conventional detector at 120 kVp (57.0 % vs. 62.2 %). The CTDIvol at 80, 100 and 120 kVp measured 4.5–5.2, 7.3–7.9 and 9.8–10.2 mGy, respectively. The IC detector at 100 kVp resulted in similar low-contrast detectability compared to the conventional detector with a 120-kVp protocol at a radiation dose reduction of 37 %. • An integrated circuit (IC) detector significantly improves the quantitative image quality • The IC detector results in a significant improvement of low-contrast detectability • Reduction of tube voltage to 100 kVp is feasible in obese patients • The IC detector holds great promise for improving patient safety

A 5.25-V-tolerant bidirectional I/O circuit has been developed in a 28-nm standard complementary metal-oxide-semiconductor CMOS process with only 0.9 and 1.8V transistors. The transistors of the I/O circuit are protected from over-voltage stress by cascode transistors whose gate bias level is adaptively controlled according to the voltage level of the I/O pad. The n-well bias level of the p-type metal-oxide-semiconductor transistors of the I/O circuit is also adapted to the voltage level of the I/O pad to prevent any junction leakage. The 5.25-V-tolerant bidirectional I/O circuit occupies 40µm×170µm of silicon area. Copyright © 2014 John Wiley & Sons, Ltd.

Due to their specific position and role in electric power systems, generator circuit breakers (GCBs) must be so developed and manufactured that they can withstand extremely high short circuit currents several times over their entire lifetime. Therefore, an accurate and efficient method for performing a coupled electromagnetic-mechanical simulation of a GCB in its full geometrical complexity is of paramount importance for daily design. This paper presents in detail a novel method for coupling of electromagnetic and dynamic mechanical analysis for GCBs. The suggested method is fast, accurate, efficient, robust, and suitable for 3-D geometries of high complexity.

The purpose of this article was to assess the effect of an integrated circuit (IC) detector for abdominal CT on image quality.In the first study part, an abdominal phantom was scanned with various extension rings using a CT scanner equipped with a conventional discrete circuit (DC) detector and on the same scanner with an IC detector (120 kVp, 150 effective mAs, and 75 effective mAs). In the second study part, 20 patients were included who underwent abdominal CT both with the IC detector and previously at similar protocol parameters (120 kVp tube current-time product and 150 reference mAs using automated tube current modulation) with the DC detector. Images were reconstructed with filtered back projection.Image quality in the phantom was higher for images acquired with the IC compared with the DC detector. There was a gradually increasing noise reduction with increasing phantom sizes, with the highest (37% in the largest phantom) at 75 effective mAs (p0.001). In patients, noise was overall significantly (p = 0.025) reduced by 6.4% using the IC detector. Similar to the phantom, there was a gradual increase in noise reduction to 7.9% in patients with a body mass index of 25 kg/m(2) or lower (p = 0.008). Significant correlation was found in patients between noise and abdominal diameter in DC detector images (r = 0.604, p = 0.005), whereas no such correlation was found for the IC detector (r = 0.427, p = 0.060).Use of an IC detector in abdominal CT improves image quality and reduces image noise, particularly in overweight and obese patients. This noise reduction has the potential for dose reduction in abdominal CT.

A two-channel integrated circuit for processing current pulses of silicon photomultiplier is based on an АБМК-1.3 analog basic array. Each channel of the integrated circuit contains a transresistance amplifier with a maximal conversion coefficient of about 5 mV/μA, regulated in a −70 dB range, and a discriminator with a threshold changeable within ±500 mV. The circuit designs of separate stages of the integrated circuit and experimental characteristics are given.

There are three types of microwave circuits which include microWave elements. The first is a discrete circuit; packaged diodes/transistors mounted in coax and waveguide assemblies. Second Hybrid MIC (Microwave Integrated Circuit); diodes/transistors and microstrip fabricated separately and then assembled. The third is MMIC (Monolithic Microwave Integrated Circuit); diodes, transistors and microstrip fabricated simultaneously. The monolithic microwave integrated circuit (MMIC) consists of diodes, transistor, microstrip transmission lines, microstrip circuits, and other circuit elements, such as lumped capacitors, resistors, etc., which have parasitic effects influence on overall system stability behavior.

This paper presents the development of a neuromorphic system for visual pattern recognition. Associative memory algorithm has been used to recognize specific patterns and the method is implemented with discrete circuit elements that use memristors as the synapse. Weight of the synapses between the inputs and output neurons are adjusted by memristors. The amount of the neural block depends on how many patterns and each block contains 30 weighted synapses connected to the output. Each input corresponding to a pixel in a 6×5 pixel image generates voltage pulses according to the pixel value. The input voltage pulses weight are then maintained by the memristors and integrated by the output neurons. Each of the output of neurons is compared with a fixed threshold voltage which will determine whether the output bit is 0 or 1. Successfully demonstration of the system has been done by training and recognizing images of numbers from 1 to 8.