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This work proposes a 2-dimensional programable SRAM-based PUF. The selection of challenge groups, orders, and sequence lengths dominates the responses with challenge-response pairs (CRPs) by order of rows $^{\mathrm {(sequence~\textrm {}length- 1)}} \times $ columns $^{\mathrm {(sequence~\textrm {}length - 1)}}$. The PUF bit cell has split word-lines with vertical and horizontal connections, the bit-lines are placed orthogonally to generate one-bit data with four cells, the entropy source is enriched to 24 transistors. The proposed PUF supports multiple data maps from a single chip. A test chip was fabricated in 65 nm CMOS technology. Under 0.8V and 20 °C (nominal point), the bit error rate reaches 3%. In a single chip, the hamming distance achieves 42.49% within the same group and different orders of challenges, and 47.32% within the different groups of challenges (when the sequence length is 5). The measured inter-hamming distance between chips is improved to 49.47%. [ABSTRACT FROM AUTHOR]

This paper presents a 12-bit multi-channel resistor–resistor-string digital-to-analog converter (RRDAC) using a shared R-string scheme for an area efficient display source driver. The proposed scheme relaxes the required equivalent resistance value of R-string of each channel by sharing a channel R-string that is simultaneously connected to the same tap of a global R-string. Thus, the overall DAC size can further be minimized while maintaining the same accuracy. That is, if the proposed scheme is implemented with the same size as the conventional RRDAC, higher accuracy can also be achieved. For the verification of shared resistor string scheme, a 12-bit RRDAC was fabricated using 0.35- $\mu$ m standard CMOS technology. Compared with the conventional RRDAC, the proposed design showed a 15% reduction in size, a DNL of 0.49 LSB and an output voltage deviation of 9. 3mV for eight different chips. Also, the area per channel was 0.0465 mm2. [ABSTRACT FROM AUTHOR]