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Though GaN HEMTs have primarily been used for power amplification, they are also well suited for receiver applications. In the front-end of receivers, non-linearities, in particular third-order intermodulation products lead to in-band signal distortion. The intermodulation distortion is primarily dominated by transconductance and its derivatives. In this paper, we report on N-polar GaN MIS-HEMTs able to simultaneously achieve high gain (12.7 dB) and excellent linearity performance (OIP3/PDC of 15 dB) for low-power receiver application at 30 GHz. With a two-tone load-pull input-bias sweep, we demonstrate that the linearity of high performance HEMTs is sensitive to bias, and we present our measurement methodology to accommodate this. [ABSTRACT FROM AUTHOR]

The dynamic range of a radio-over-fiber (RoF) link is fundamentally limited by the linearity of electro-optic modulators. Silicon photonic (SiP) processes offer significant potential for integration, but the plasma dispersion effect impacts the realizable spur-free dynamic range (SFDR). This article analyzes the underlying source of nonlinearity in SiP Mach–Zehnder modulator (MZM) and demonstrates fundamental limitations on intermodulation distortion. A SiGe low-noise distributed driver is co-designed for the SiP MZM to linearize and extend the bandwidth over which the SFDR remains high. The RoF transmitter achieves 1–20 GHz bandwidth and an SFDR of 109 dB $\cdot $ Hz2/3 at 11 GHz. To the best of our knowledge, this is the highest SFDR demonstrated for a SiP technology without incorporating predistortion. [ABSTRACT FROM AUTHOR]

This paper demonstrates generalized code-selective filters for code-pass and code-reject signal processing at RF. A code-reject scheme using a quarter-wave ($\lambda /4$) impedance transformation is also demonstrated to overcome tradeoffs of insertion loss (IL) and linearity compared to series band-reject $N$ -path filters. A 45-nm CMOS SOI implementation consumes a power of 9.32 mW from 1 to 1.8-V supplies at the frequency of 0.35–1.1 GHz and the chip area is 1.73 mm2. The measured transmit rejection is up to 22.6 dB with 4-dB IL. The in-band third-order-intercept point (IIP3) is up to 22.6 dBm and noise figure (NF) of 4–6 dB depending on the applied codes. [ABSTRACT FROM AUTHOR]

A channel-selecting low-noise amplifier (CS-LNA) with blocker filtering is presented for a SAW-less diversity path receiver (RX) in frequency-division duplexing cellular systems. A hybrid N-path bandpass filter/band-reject filter (BPF/BRF) feedback network is applied to the LNA to create close-in reject bands around the passband to suppress transmit leakage and improve the out-of-band (OOB) input-referred third-order intercept point (IIP3). Control of the frequency and depth of the reject bands is demonstrated with analysis and simulation. A gm2{\mathchar"702D}gm3 cancellation linearization is applied to improve the in-band (IB) linearity. Adaptive LO swing and silicon-on-insulator (SOI) thick-oxide devices are demonstrated to improve the power-handling capability. The proposed CS-LNA is implemented in 32-nm CMOS SOI and operates from 0.4 to 6 GHz with the maximum rejection larger than 60 dB and power-handling capability up to 17 dBm. The prototype demonstrates an OOB IIP3 of 36 dBm and IB IIP3 of 10 dBm at 1 GHz. To the authors’ knowledge, this is the highest blocker rejection, power-handling capability, linearity, and the widest tuning range for an LNA with tunable filtering. [ABSTRACT FROM PUBLISHER]

A tunable N-path filter with more than one decade tuning range is demonstrated to address transmit (TX) leakage in a surface-acoustic-wave-less diversity path receiver for frequency-division duplexing cellular systems. The proposed filter simultaneously creates a reject band and passband anywhere from 0.2 to 3.6 GHz to suppress TX leakage while minimizing insertion loss of the receive signal and is implemented in 45-nm CMOS silicon-on-insulator. Measurements show the 3-dB bandwidth of the passband is greater than 80 MHz with an independently tunable reject band, providing the ultimate rejection is from 33 to 41 dB while the passband insertion loss is between 2.6 dB and 4.3 dB over the tuning range. The proposed filter offers 29-dBm out-of-band (OOB) third-order input-intercept power (IIP3) and 22-dBm in-band (IB) IIP3 with a 10-dBm blocker 1-dB compression point (B1dB). To the authors’ knowledge, this is the highest B1dB, IB IIP3, and OOB IIP3 for a CMOS tunable filter. [ABSTRACT FROM PUBLISHER]

A 10-GHz outphasing modulator is implemented in a 45-nm CMOS silicon-on-insulator process. The modulator is designed to provide high linearity and can operate at high data rates by using 256-QAM while maintaining low error vector magnitude (EVM). Four high-speed 10-bit digital-to-analog converters (DACs) are integrated with dual in-phase and quadrature upconverters. To deliver high output power to an off-chip power amplifier, stacked field-effect transistor current buffers are used to isolate the modulator from the load and mitigate device breakdown. As a result, this modulator delivers 23 dBm to a differential 100-\Omega load. The high-resolution DACs provide a fine control of the phase between the outphased signals and support more than 60 dB of dynamic range and power steps smaller than 1 dB over the entire output power range. The outphasing modulator demonstrates an EVM of 2.2% at 80 Mbit/s and an EVM of 3.4% at 1.1 Gbit/s for 256-QAM. To our knowledge, this is the first demonstration of an outphasing modulator operating above 1 Gb/s. [ABSTRACT FROM PUBLISHER]

A 10 bit current-steering, digital-to-analog converter (DAC) is presented that delivers 6 VPP into a 100 Ω differential load. To realize high-voltage swings using fineline CMOS, a stacked-FET buffer is used to isolate the current source from the output load. The stacked-FET buffer degrades the linearity of the DAC. This work presents a Volterra analysis to capture the frequency-dependent behavior of the stacked-FET circuit that can be cascaded to quantify the linearity of an N-device stack. The power DAC is implemented in 45 nm CMOS SOI and the measured differential nonlinearity (DNL) and integral nonlinearity (INL) is better than 0.4 and 0.6 LSB, respectively. The DAC consumes 476 mW and achieves a peak SFDR of 73 dB and a minimum IM3 of -69 dBc. This DAC demonstrates the largest output swing and highest power efficiency for a high-resolution (>8 bit), high-speed (>100 MS/s) DAC. [ABSTRACT FROM PUBLISHER]

Analytical techniques to determine the linearity and spur-free dynamic range (SFDR) for phased array receivers are presented. The proposed method eliminates the need for circuit-level simulation of intermodulation distortion in an N-element receiver by characterizing the array SFDR from the SFDR for a single receive channel. The analysis separates the relative impact of array factor, circuit architecture and channel linearity to assess the spatial sensitivity of the receiver to jamming signals. The proposed techniques are applied to a comparison of RF phase-shifting and LO phase-shifting receivers. RF phase-shifting architectures are shown to offer more uniform jammer rejection over the beam-scanning range given the same receiver linearity constraints. [ABSTRACT FROM AUTHOR]