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Current sourceinverters (CSIs) require power switches with first quadrant current conduction and gate-controlled output characteristics as well as reverse blocking capability. Experimental demonstration of a SiC monolithic reverse blocking transistor (MRBT) suitable for CSI applications is described in this letter. The proposed device is based on the integration of a SiC JBS diode with a SiC power mosfet on the same chip. The cathode of the SiC JBS diode is connected to the drain of the SiC power mosfet by their common N+ substrate. The proposed device structure creates a novel SiC-based unipolar single-chip three-terminal transistor with reverse blocking capability. The measured characteristics of a 1.2 kV 4H-SiC MRBT, fabricated in a commercial six-inch wafer foundry, are reported in this letter. The devices show a diode-like on-state characteristic with a low knee voltage of 1.3 V and an on-state voltage drop of 2.8 V at 5 A. The measured reverse transfer capacitance and output capacitance for the MRBT at a drain bias of 2 and 1000 V are a factor of ∼3x and ∼1.6x smaller than the measured values for the internal mosfet device. Switching measurements show a 12% reduction in the gate-drain charge for the MRBT compared with the internal mosfet which is favorable for reducing switching losses. [ABSTRACT FROM AUTHOR]

The electrical characteristics of 2.3-kV 4H-SiC power Junction Barrier Schottky Field-Effect Transistors (JBSFETs) fabricated with 55-nm gate oxide thickness are reported as a function of temperature for the first time. The behavior of three cell topologies (linear, hexagonal, and octagonal) is compared. Excellent JBSFET characteristics are demonstrated up to 150 °C. The ON-resistance was found to increase by 45% from 25 °C to 150 °C for the linear and hexagonal cell layouts, which is much less than the 100% increase previously reported for silicon carbide (SiC) power MOSFETs. The threshold voltage decreases with temperature but remains above 1.2 V even at 150 °C for all cases. The third-quadrant current flow via the integrated JBS diode is confirmed to suppress body diode conduction at all temperatures. The leakage current remains below $1~\mu \text{A}$ even at 150 °C despite the presence of the Schottky contact in the JBSFET structure due to optimum JBS diode design. The octagonal cell topology is shown to exhibit the best figures of merit (FOMs) FOM[ $ \mathrm{R}_{ \mathrm{\scriptscriptstyle ON}}{}^{\ast } \mathrm{C}_{ \mathrm{\scriptscriptstyle GD}}$ ] and FOM[ $ \mathrm{R}_{ \mathrm{\scriptscriptstyle ON}}{}^{\ast } \mathrm{ Q}_{ \mathrm{\scriptscriptstyle GD}}$ ] even at elevated temperatures. The observed device behavior is explained using device analytical modeling. The analytical modeling reveals that the reduced rate of increase in ON-resistance with temperature for the 2.3-kV SiC JBSFETs is due to the relatively large source contact resistance produced by the lower (900 °C) contact anneal temperature. The lower anneal temperature is required to simultaneously make the Schottky contact for the JBS diode. [ABSTRACT FROM AUTHOR]

Planar-gate 2.3 kV 4H-SiC power MOSFETs were successfully fabricated in a commercial foundry with the gate oxide thickness reduced from 55 to 27 nm for the first time. Results of numerical simulations demonstrate acceptable gate oxide electric field despite the increased blocking voltage. For a gate bias of 15 V, the measured specific ON-resistance (${R}_{\mathrm {ON},\text {sp}}$) and high-frequency figures-of-merit (FOM[ ${R}_{\mathrm {ON}} \times {C}_{\text {gd}}$ ], FOM[ ${R}_{\mathrm {ON}} \times {Q}_{\text {gd}}$ ]) were improved by a factor of $1.3\times $ by reducing the gate oxide thickness even at the larger blocking voltage. Analytical modeling shows that the channel and accumulation layer resistances are still important contributors even at this larger blocking voltage capability. Operating the 27 nm gate oxide devices with the commonly accepted ON-state gate oxide electric field of 4 MV/cm for reliable operation makes the ${R}_{\mathrm {ON},\text {sp}}$ and FOMs for the 27 nm gate oxide case 10% worse than the 55 nm gate oxide case. However, the reduced gate bias of 11 V for the 27 nm gate oxide case reduces input switching power loss in half from a gate drive perspective. In addition, operation at this gate bias makes the saturation current for the 27 nm gate oxide devices three times smaller than for the conventional devices operating at a gate bias of 20 V, which will proportionally increase short-circuit withstand time. [ABSTRACT FROM AUTHOR]

Planar 650-V 4H-silicon carbide (SiC), inversion-channel, 55-nm gate oxide junction barrier Schottky field effect transistors (JBSFETs) with three types of cells are compared in this article for the first time. Devices with linear, hexagonal, and octagonal layouts were fabricated in a commercial foundry. The JBS diode was integrated within each cell type. The Schottky contact width for the JBS diode was adjusted to optimize third-quadrant ON-state voltage drop to below 2.5 V for each cell type to ensure by-passing the body diode while maintaining good blocking characteristics in the first quadrant. The hexagonal cell case was the only one whose breakdown voltage (560 V) fell below the 650-V rating. The highest breakdown voltage (710 V) was observed with the octagonal cell layout with a low leakage current of 10 nA at 600 V. The lowest specific ON-resistance was observed for the hexagonal cell design. However, its gate–drain charge was twice that of the conventional linear cell design and four times that of the octagonal cell design. The data from this work demonstrate that the best overall performance for the 650-V SiC, inversion-channel, 55-nm gate oxide junction barrier Schottky field effect transistors is achieved by using the octagonal cell design. [ABSTRACT FROM AUTHOR]

Advanced SiC planar-gate power MOSFETs have been successfully manufactured in a 6-inch commercial foundry with device structures optimized for operation with gate drive voltage of 10 V, compatible with gated drive voltage for Si superjunction products. The electrical characteristics of three advanced SiC MOSFET options are described in this article and compared with those of a state-of-the art Si superjunction MOSFET. The new advanced SiC power MOSFETs are demonstrated to exhibit superior on-state and switching losses with significantly better body-diode reverse recovery performance. Their short-circuit withstand time is also found to be significantly longer than typical commercially available planar-gate SiC power MOSFETs. These improved characteristics make the advanced SiC power MOSFETs suitable replacements for Si superjunction transistors to enhance high frequency circuit performance. [ABSTRACT FROM AUTHOR]

The performance of four cell topologies is compared for 2.3-kV 4H-SiC power MOSFETs fabricated in a commercial 6-in foundry. The devices were simultaneously manufactured with the same channel length (0.5 μm), JFET width (1.1 μm), and gate oxide thickness (55 nm) for comparison. In addition, an octagonal cell design with a JFET width of 1.5 μm was included for comparison. The square and hexagonal cell designs had the lowest specific ON-resistance, but their breakdown voltage was found to be reduced below 2.3 kV due to sharp cell corners. The smallest reverse transfer capacitance and gate charge were observed for the octagonal cell design with significantly larger (~5 ×) values for the square and hexagonal designs. The high-frequency figure-of-merit HF-FOM [RON* Crss] for the octagonal cell design was 3.5 × superior to the hexagonal and square cells and 1.5 × better than the linear cell. Its high-frequency figure-of-merit HF-FOM [RON* Qgd] was 1.5 × superior to the hexagonal and square cells and 1.2 × better than the linear cell. This work demonstrates that the square and hexagonal cells are the best for low-frequency applications, whereas the octagonal cell design is the most suitable for achieving the best high-frequency performance of 2.3-kV 4H-SiC power MOSFETs. [ABSTRACT FROM AUTHOR]

The measured electrical characteristics of 600 V planar-gate inversion-channel 4H-SiC power MOSFETs fabricated in a 6 inch commercial foundry with 27 nm gate oxide thickness are compared with 55 nm gate oxide devices. The High-Frequency Figures-of-Merit (HF-FOMs) of the SiC MOSFETs with 27 nm gate oxide were found to surpass that of commercially available 600 V P7 Si CoolMOS products for the first time. Statistical parametric distribution data and wafer-maps for the 27 nm devices are provided to demonstrate that excellent yield and uniformity can be achieved with the reduced gate oxide thickness. These devices can be operated at 15 V gate bias compatible with IGBT gate drivers. [ABSTRACT FROM AUTHOR]

This letter compares the measured electrical characteristics of 600 V planar-gate inversion-channel 4H-SiC power MOSFETs fabricated with four different cell topologies (Linear, Square, Hexagonal, and Octagonal) for the first time. The High-Frequency Figures-of-Merit (HF-FOMs) of these devices were compared with the commercially available SiC device and the Si CoolMOS product. It was found that the HF-FOMs of the 600-V SiC product and our fabricated conventional Linear cell device are much worse in comparison to the Si CoolMOS product. However, the 600 V SiC power MOSFET with comparable performance to the Si CoolMOS product could be achieved by using the Octagonal cell topology. [ABSTRACT FROM AUTHOR]

The authors of the above paper would like to report an error concerning the Rohm product mentioned in the Introduction, and discussion associated with. The Rohm product (R6020JNZ4) in the original paper is a Silicon MOSFET and not a SiC product. Our original paper stated that “The commercial SiC ROHM 600V product has $2.6\times$ inferior HF-FOM[Ron *Qgd] compared with Si CoolMOS™ product creating a major deterrent to market penetration.” We would like to retract this statement because it was based on the incorrect Rohm product (R6020JNZ4). The authors sincerely regret the error in our original paper. [ABSTRACT FROM AUTHOR]