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In this paper, a detailed evaluation of sub-10-nm n-/p-type GaSb–InAs double-gate tunneling FETs (TFETs) is presented. Source underlapping is shown to achieve lower subthreshold swing (SS) in both n- and p-type GaSb–InAs TFETs and is verified with the analytical treatment. The impact of parameter variations on the performance of underlapped TFETs is investigated through atomistic, 2-D ballistic simulations using self-consistently coupled nonequilibrium Green’s function-Poisson approach. Variations in underlap length, underlap doping, fin thickness, and temperature are comprehensively studied. It is shown that the underlap length of 6 nm is optimal for achieving low SS and it is found that the underlapped TFETs can maintain sub-60-mV/decade SS even when 3-nm fin thickness is relaxed by 40%. We also study the potential of TFETs in ultralow-power and high-density dynamic memories. A novel 4T gain cell embedded Dynamic Random Access Memory (e-DRAM) is proposed, which utilizes the low-leakage current of the source-underlapped TFETs to improve the data-retention time to 25 \mu \texts at V\mathrm {DD}=0.35 V, thereby enabling the prospects of e-DRAM at nanoscale gate lengths operating at ultralow supply voltages. [ABSTRACT FROM PUBLISHER]

A 6T SRAM design at a sub-10-nm node calls for carefully designed transistors so that new leakage mechanisms, such as direct source-to-drain tunneling (DSDT) and short channel effects that lead to I\mathrm{\scriptscriptstyle ON}/I\mathrm{\scriptscriptstyle OFF} degradation, are kept under control. In this paper, we explore asymmetric underlap for mitigating DSDT, thermionic leakage, and for improving I\mathrm{\scriptscriptstyle ON}/I\mathrm{\scriptscriptstyle OFF} of double-gate FinFETs. We demonstrate that for 6T SRAMs, asymmetric underlapped n-FinFETs are superior to symmetric underlap/overlap in improving access time and leakage power. We model the atomistic nature of sub-10-nm FinFET channels, quantum confinement, subband nonparabolicity, and anisotropy latent at such length scales using quantum physics-based simulators instead of the conventional semiclassical, drift-diffusion-based Technology Computer Aided Design tools. Using a device/circuit/system-level codesign approach consisting of NEMO5 quantum mechanical device simulations, HSPICE circuit simulations of a 6T SRAM bit cell, and a system-level analysis of a 8-kB L1 and 4-MB L2 cache, we show that the adoption of optimized asymmetric underlapped n-FinFETs can offer up to 6.5% improvement in L1 cache access times and a 2.3-mW reduction in L2 cache leakage power, while delivering noise margins close to symmetric underlapped n-FinFET-based caches. [ABSTRACT FROM PUBLISHER]