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Asymmetric Underlapped Sub-10-nm n-FinFETs for High-Speed and Low-Leakage 6T SRAMs.
- Source :
-
IEEE Transactions on Electron Devices . Mar2016, Vol. 63 Issue 3, p1034-1040. 7p. - Publication Year :
- 2016
-
Abstract
- A 6T SRAM design at a sub-10-nm node calls for carefully designed transistors so that new leakage mechanisms, such as direct source-to-drain tunneling (DSDT) and short channel effects that lead to I\mathrm{\scriptscriptstyle ON}/I\mathrm{\scriptscriptstyle OFF} degradation, are kept under control. In this paper, we explore asymmetric underlap for mitigating DSDT, thermionic leakage, and for improving I\mathrm{\scriptscriptstyle ON}/I\mathrm{\scriptscriptstyle OFF} of double-gate FinFETs. We demonstrate that for 6T SRAMs, asymmetric underlapped n-FinFETs are superior to symmetric underlap/overlap in improving access time and leakage power. We model the atomistic nature of sub-10-nm FinFET channels, quantum confinement, subband nonparabolicity, and anisotropy latent at such length scales using quantum physics-based simulators instead of the conventional semiclassical, drift-diffusion-based Technology Computer Aided Design tools. Using a device/circuit/system-level codesign approach consisting of NEMO5 quantum mechanical device simulations, HSPICE circuit simulations of a 6T SRAM bit cell, and a system-level analysis of a 8-kB L1 and 4-MB L2 cache, we show that the adoption of optimized asymmetric underlapped n-FinFETs can offer up to 6.5% improvement in L1 cache access times and a 2.3-mW reduction in L2 cache leakage power, while delivering noise margins close to symmetric underlapped n-FinFET-based caches. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 00189383
- Volume :
- 63
- Issue :
- 3
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Electron Devices
- Publication Type :
- Academic Journal
- Accession number :
- 113411498
- Full Text :
- https://doi.org/10.1109/TED.2015.2512227