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Monolithic integration of junction barrier-controlled Schottky (JBS) diode with SiC MOSFET (termed JMOS) offers unique advantages. However, the short-circuit (SC) ruggedness issue stands in the way of the development of the conventional JMOS. The purpose of this numerical study is to investigate a new 4H-SiC JMOS with a self-pinching (SP) structure formed in the JFET region (termed SP-JMOS). The SP structure features that an N-type current spread layer is sandwiched between the P+ layer and the buried P-shield layer, forming a lateral JFET channel. In the forward conduction state, the lateral JFET channel self-pinches off and clamps the potential, thus limiting the saturation current of the device. In the blocking state, both the P+ layer and the buried P-shield layer collaboratively shield the Schottky contact and the SiC/SiO2 interface from a high electric field for long-term reliable operation. Numerical simulation results show that the proposed SP-JMOS not only withstands a roughly $2.6\times $ longer SC withstanding time than that of the conventional JMOS, but also shows an ultralow oxide electric field in the SP-JMOS. [ABSTRACT FROM AUTHOR]

The Smart Discrete concept which monolithically integrates a vertical high-voltage power device with low-voltage smart circuits has been widely adopted in silicon world for many years and may bring similar benefits to SiC world. For example, it is highly desirable to integrate a gate driver circuit onto a high-voltage SiC thyristor for ultra-fast turn-on. However, the electrical isolation between the vertical high-voltage power device and the low-voltage circuit elements remains a major technical challenge for silicon, and even more so for SiC due to the very limited processing options. In this article, we propose a combination of shallow junction isolation (JI) and partial dielectric isolation (DI) for high-voltage 4H-SiC smart thyristor, which is monolithically integrated with low-voltage nMESFET circuits. The characterization of fabricated devices and analysis of leakage currents across the isolation structure have been done to experimentally verify the feasibility of the isolation method. 8 V parasitic lateral NPNP thyristor between a 6.3 kV 4H-SiC thyristor and isolation moats, 175 V lateral PNP transistor between the passive resistor and isolation moats, and 10 V lateral reverse-biased p-n diode between nMESFET and isolation moats are experimentally demonstrated. [ABSTRACT FROM AUTHOR]

A 600 V-rated insulated gate bipolar transistor (IGBT) with improved turn-on transient characteristics is proposed and investigated by simulation. The proposed IGBT features a built-in voltage-clamping structure. The floating ${p}$ -body adjacent to the trench gate is clamped at an appropriately high voltage before turn-on. This slows down the hole accumulation process in the floating p-body during turn-on transient, and thus the self-charging displacement current through the gate capacitance is reduced. The increasing rate for the gate voltage (dVGE/dt) is then reduced. As a result, the proposed IGBT achieves a 25% decrease in collector current ($I_C$) overshoot and 34% decrease in dIC/dt, when compared with the conventional IGBT with the same turn-on loss (EON), at IC = 250 A/cm2 under hard-switching. Its fabrication process is compatible with conventional trench IGBT. [ABSTRACT FROM AUTHOR]

In this paper, we present a lateral injection enhanced insulated gate bipolar transistor (LIEGT) and investigate its mechanism. The LIEGT features a recessed trench at the cathode side of the drift region formed by LOCal oxidation of silicon (LOCOS) process. The recessed trench suppresses holes being extracted and enhances the electron injection, thus contributing to a very low loss in the ON-state. The ON-state voltage (${V}_{ \mathrm{\scriptscriptstyle ON}}$) of the LIEGT is reduced by 24% at the current density of 200 A/cm2 and the saturation current is 40% higher than that of the conventional lateral insulated gate bipolar transistor (LIGBT). The LIEGT exhibits an improved tradeoff between ${V}_{ \mathrm{\scriptscriptstyle ON}}$ and turnoff loss (${E}_{ \mathrm{\scriptscriptstyle OFF}}$). For the same ${V}_{ \mathrm{\scriptscriptstyle ON}}$ , the ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ is decreased by 38% compared with that of the conventional LIGBT. [ABSTRACT FROM AUTHOR]

A novel ultrafast and low-loss lateral injection-enhanced gate transistor (LIEGT) is proposed and investigated by simulation. The device features a MOS-controlled shorted anode (MCSA) and a bias voltage (${V}_{{AG}}$) applied between the anode trench gate (ATG) and the anode electrode. The n+ anode is shorted to the N-buffer through the MOS channel around the ATG when the MCSA is activated with ${V}_{{AG}} > {V}_{{th}}$ during turn-off and blocking states, and thus the p+ anode/N-buffer junction is unactivated. The MCSA LIEGT turns off as fast as a unipolar device by optimizing the time gap to activate the MCSA before turning off the cathode trench gate (CTG). The activated MCSA would deactivate hole injection from the anode side and synchronously quickly extract the electrons from the N-drift, which improves the switching speed and dramatically decreases the turn-off energy loss (${E}_{ \mathrm{\scriptscriptstyle OFF}}$). In the blocking state, the MCSA LIEGT achieves a MOS breakdown mode instead of an open base p-n-p bipolar breakdown mode. Thus, the breakdown voltage (BV) is not only improved but also independent of the p+ anode doping concentration. In the forward conduction state with ${V}_{{AG}} = {0}$ , the MCSA is unactivated and hence the MCSA LIEGT operates like a conventional LIEGT without deteriorating the on-state voltage drop (${V}_{ \mathrm{\scriptscriptstyle ON}}$). Compared with the conventional LIEGT, the proposed device decreases ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ by 88% and improves the BV by 13% at the same ${V}_{ \mathrm{\scriptscriptstyle ON}}$. Importantly, ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ is almost independent of ${V}_{ \mathrm{\scriptscriptstyle ON}}$. [ABSTRACT FROM AUTHOR]

A novel carrier stored (CS) SOI lateral insulated gate bipolar transistor (LIGBT) with ultralow on-state voltage drop (${V}_{ \mathrm{\scriptscriptstyle ON}}$) and high current capability is proposed and its electronic performance is investigated by simulation. The device features the CS layer and the trigate (TG) structure, named TGCS LIGBT. The CS effect in the on-state delivers an ultralow ${V}_{ \mathrm{\scriptscriptstyle ON}}$. The TG is employed to increase the channel density and modulate the current distribution, further reducing the ${V}_{ \mathrm{\scriptscriptstyle ON}}$ and achieving high current capability. Moreover, TG assists in depleting the highly doped CS layer, which enhances the conductivity modulation and maintains high breakdown voltage. The extended P+ in the comb-shaped P+ region provides a low-resistance hole current path, and thus enhances the latch-up immunity. At the same turn-off loss, the TGCS LIGBT reduces the ${V}_{ \mathrm{\scriptscriptstyle ON}}$ by 32.5% and 36.4% compared with the tridimensional channel (TC) LIGBT and the conventional (Con). LIGBT, respectively. The TGCS LIGBT exhibits high current capability, which has an improvement of 151% and 26.8% compared with those of the Con. LIGBT and the TC LIGBT, respectively. The TGCS LIGBT shows a little better short-circuit capability than does the Con. LIGBT. [ABSTRACT FROM AUTHOR]

A 600-V snapback-free fast-switching silicon-on-insulator lateral insulated gate bipolar transistor with an embedded self-biased n-MOS (SBM) is proposed and investigated by simulations. The proposed device features an n-MOS which consists of the N+ anode, p-layer, N-buffer, and the anode trench gate (ATG) embedded between the P+ anode and N+ anode. It is worth noting that the ATG is driven by the anode, without any additional control circuits. At the initial conduction stage, p-layer/N-buffer junction acting as electron barrier contributes to snapback-free with a reduced cell pitch. Simultaneously it provides an extra built-in path to extract electrons at the turn-OFF stage, which hence reduces the turn-OFF energy loss (${E} _{ \mathrm{\scriptscriptstyle OFF}}$) and increases the switching speed. Furthermore, the hole leakage current of the SBM LIGBT in the blocking state is suppressed due to the electron accumulation/inversion formed along the sidewall of the ATG, avoiding triggering the P+NP transistor and thus increases the breakdown voltage by 11% in comparison with that of the conventional LIGBT. Simulation results show that the SBM LIGBT reduces ${E} _{ \mathrm{\scriptscriptstyle OFF}}$ by 31% and 43% compared to the conventional LIGBT with the same on-state voltage drop (${V} _{ \mathrm{\scriptscriptstyle ON}}$), at the load current of 100 and 200 A/cm2, respectively. [ABSTRACT FROM AUTHOR]

In this paper, a novel reverse conducting insulator gate bipolar transistor (RC-IGBT) with discontinuous field-stop (DFS) layer is proposed and investigated. The DFS increases the distributed resistance near the collector side in the unipolar mode; and thus, eliminates the snapback phenomenon with a reduced half-cell pitch of $60~\mu \text{m}$. In the blocking state, the depletion region is pinched off by the DFS and thus punchthrough is avoided, ensuring high breakdown voltage of 1200 V. The DFS RC-IGBT shows higher short-circuit ruggedness and increases the short-circuit duration time by 30% compared with the conventional RC-IGBT due to the decreased base transport factor. The proposed structure also achieves better tradeoff between turn-OFF loss and forward voltage drop. For the same forward voltage drop, the turn-OFF loss is reduced by 30%. [ABSTRACT FROM AUTHOR]

An ultra-low specific ON-resistance ( R\text {on,sp} ) LDMOS is proposed and investigated by simulation in this letter. It features an extended tri-gate, a trench source, and a trench drain. in the on-state, multi-plane electron accumulation layers (MALs) and hence multiple ultra-low resistance current paths are formed along the bottom surface and side wall of the extended tri-gate. In the OFF-state, the extended gate assists in depleting the drift region and thus increases the doping concentration of the drift region ( Nd) . Both contribute to an ultralow ON-resistance. Moreover, the combined structure of the extended gate and tri-gate enhances the transconductance ( gm) of the device. Additionally, the trench source and the trench drain shorten the current paths. As a consequence, both the current under the extended tri-gate and the total current increase. The performance of the MAL LDMOS is superior to that of the current state of art. Compared with the 70 V conventional LDMOS (Con. LDMOS) with the same dimension, the MAL LDMOS reduces the R\text {on,sp} by 90% and doubles the gm owing to the multi-plane accumulation layers. The MAL LDMOS maintains nearly the same breakdown voltage as the Con. LDMOS. [ABSTRACT FROM AUTHOR]

The high ON-resistance and the limited breakdown voltage (BV) are the two major issues for the p-channel lateral double-diffused MOSFET (pLDMOS). To solve the two issues, an ultralow specific ON-resistance ( R\mathrm{\scriptscriptstyle ON,\textrm {sp}} ) pLDMOS with improved BV is proposed and investigated by simulation. It features an extended gate (EG) with accumulation effect over the drift region and a P+ floating layer (PFL) in the N-sub. In the ON-state, the EG induces the hole accumulation layer along the drift region surface, providing an ultralow-resistance conducting path. This accumulation-type current transport mode makes R\mathrm{\scriptscriptstyle ON,\textrm {sp}} almost independent of the drift region doping concentration ( Nd ) and contributes to a much lower R\mathrm{\scriptscriptstyle ON,\textrm {sp}} , which greatly breaks through the silicon limit of R\mathrm{\scriptscriptstyle ON,\textrm {sp}}\propto \textrm {BV}^{2.5} . In the OFF-state, the EG not only modulates the surface electric field ( E -field) distribution to enhance the BV, but also helps deplete the drift region to increase the optimized Nd , and thus further reduce R\mathrm{\scriptscriptstyle ON,\textrm {sp}} . Moreover, the PFL is not depleted, and thus equipotential in the lateral direction. Therefore, the PFL not only modulates the bulk E$ -field distribution at the source and drain sides but also introduces an additional vertical diode to sustain a higher BV. Owing to the effects mentioned above, the simulated results show that the EG PFL pLDMOS decreases R\mathrm{\scriptscriptstyle ON,\textrm {sp}} by 68% and increases the BV by 47% compared with the conventional pLDMOS. [ABSTRACT FROM AUTHOR]