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The additional implanted channel-dopant layer of depletion-mode (DM) MOSFETs induces, at the same time, two main currents, namely, an accumulation current at the channel surface and a neutral-region current flowing deep in the implanted buried layer. In particular, the neutral-region current causes the normally-on condition of DM MOSFETs. These two currents dominate drain–source current alternatively depending on the bias conditions. To model the measured features of a DM MOSFET, a compact model is developed by considering also the complete vertical potential distribution from the surface to the bottom of the additional implanted channel-dopant layer. The potential distribution is self-consistently obtained by solving the Poisson equation. It is further demonstrated that a major development task is the correct coupling between Vds and Vbs contributions, which is needed to describe the specific features of the DM MOSFET accurately. [ABSTRACT FROM AUTHOR]

In this paper, a compact model for the negative bias temperature instability (NBTI) is developed by considering the interface-state generation and the hole-trapping mechanisms. This model shows accurate reproduction of the threshold voltage (Vth) degradations measured from samples fabricated with different dielectric materials as well as processes. A total of eight model parameters are introduced for describing the different degradation origins. The parameter values are verified to exhibit universal properties as a function of the electrical field within the gate oxide (Eox). By implementing the universal NBTI model into the compact model HiSIM, the dynamic NBTI effect and circuit performance degradation can be predicted. [ABSTRACT FROM PUBLISHER]

The reported compact SOI-MOSFET model hiroshima university starc igfet model-silicon on thin buried oxide (HiSIM-SOTB) has been developed for devices with ultrathin silicon on insulator (SOI) and buried oxide (BOX) layers. The potential distribution determined by the Poisson equation is accurately solved with the Newton iteration method across the SOI layer and in the substrate on the backside of the BOX for source and drain side of the device. All charges including accumulation and inversion charges on both side of the BOX are explicitly considered in the Poisson equation. It is found that different from the double-gate MOSFET, the influence of the impurity concentration of the bulk substrate below the BOX must be also explicitly considered to capture all measured properties of the silicon on thin buried oxide (SOTB) MOSFET. A further modeling challenge of the thin SOI and BOX layers, which had to be overcome, is that charge neutrality is not independently preserved at the front-gate oxide or at BOX side, but only totally within the whole device. Additionally it is found that, due to the consistent potential- and charge-based model formulation, the developed HiSIM-SOTB model can reproduce not only TCAD and measured SOTB device data but is even capable to predict the effects of structural variations, including the limiting case of the double-gate MOSFET structure. [ABSTRACT FROM PUBLISHER]