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We report high-performance amorphous Indium-Gallium-Zinc-Oxide nanowire field-effect transistors ($\alpha $ -IGZO NW-FETs) featuring an ultrascaled nanowire width (${W}_{{\mathrm {NW}}}$) down to ~20 nm. The device with 100 nm channel length (${L}_{{\mathrm {CH}}}$) and ~25 nm ${W}_{{\mathrm {NW}}}$ achieves a decent subthreshold swing (SS) of 80 mV/dec as well as high peak extrinsic transconductance (${G}_{m,{\mathrm {ext}}}$) of $612~\mu S/\mu \text{m}$ at a drain–source voltage (${V}_{{\mathrm {DS}}}$) = 2 V ($456~\mu S/\mu \text{m}$ at ${V}_{{\mathrm {DS}}}$ = 1 V). The good electrical properties are enabled by using an ultrascaled 5 nm high- ${k}$ HfO2 as the gate dielectric, a water-free ozone-based atomic layer deposition (ALD) process, and a novel digital etch (DE) technique developed for indium-gallium-zinc-oxide (IGZO) material. By using low-power BCl3-based plasma treatment and isopropyl alcohol (IPA) rinse in an alternating way, the DE process is able to realize a cycle-by-cycle etch with an etching rate of ~1.5 nm/cycle. The scaling effects on device performance have been analyzed as well. It shows that the downscaling of ${W}_{{\mathrm {NW}}}$ improves the SS notably without sacrificing ON-state performance, and the shrinking of ${L}_{{\mathrm {CH}}}$ boosts the ${G}_{m,{\mathrm {ext}}}$. The ultrascaled $\alpha $ -IGZO NW-FETs could play an important role in applications where high performance and high density are highly desired. [ABSTRACT FROM AUTHOR]

We investigate the effect of channel layer thickness on effective mobility (μeff) in the sub-10-nm regime of amorphous indium–gallium–zinc–oxide thin-film transistors (α-IGZO TFTs). TFT devices with extremely scaled channel thickness tα-IGZO of 3.6 nm were realized, exhibiting low subthreshold swing (SS) of 74.4 mV/decade and the highest effective mobility μeff of 34 cm2/V ⋅ s at a carrier density NCarrier of ~ 5 × 1012 cm−2 for any kind of α-IGZO TFTs having sub-10-nm tα-IGZO. No significant degradation of μeff is observed as α-IGZO thickness reduced from 6 to 3.6 nm. By scaling down the channel length LCH to 38 nm, high extrinsic transconductance (Gm, max) of 125 μs/μm (at VDS of 1 V) and ON-state current ION of 350 μA/μm at VGS – VT of 3 V with VDS of 2.5 V are achieved. [ABSTRACT FROM AUTHOR]

We report high performance amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transis- tors (TFTs) with 10 nm atomic-layer-deposited HfO2 as the gate dielectric, achieving subthreshold swing (SS) of 70.2 mV/decade, high effective mobility (μeff) of 55.3cm2/V⋅s at an inversion carrier density (Ninv) of 5 × 1012 cm−2, and large ION/IOFF of > 109. Furthermore, very good device-to-device uniformity has been confirmed by the statistical distribution of SS and maximum transconductance (Gm, max) measured from 20 pristine TFT devices. This a-IGZO TFT has immense potential for the ultrafast and low power electronic devices for next-generation cost-effective emissive display, image sensing, and hardware for artificial intelligence (AI). [ABSTRACT FROM AUTHOR]

The analog resistive switching (RS) characteristics in 2-D polycrystalline (poly-) molybdenum disulfide (MoS2) field-effect transistors (FETs) enable new electronic devices capable of emulating biological synaptic behaviors. In 2-D poly-materials, grain boundary (GB)-induced trap states are of major significance to RS behaviors. However, there is still a lack of appropriate compact models that capture accurate physical mechanisms. Therefore, we developed a surface potential-based compact model, based on the theories of the GB energy barrier and space charge limited current (SCLC). By calibrating to experimental data of MoS2, the physical parameters are extracted, and the model explains the scaling behaviors of channel lengths and grain sizes. Due to the electric-field-induced defect redistribution, the energy barrier modulation at a single-GB (e.g., intersecting GB) quantitatively matches the reported experiments. Moreover, the possible SCLC-based RS behavior is also investigated. Furthermore, we have optimized the set/reset process and simulated the postsynaptic current (PSC) with a tunable potentiation (or depression) process, and then the gate voltage dependence and statistical effects on RS and PSC have been investigated. Thus, this model provides important devices physics insights of 2-D poly-materials and it guides device design, fabrication, and material engineering, to meet the requirements of the future neuromorphic computing application. [ABSTRACT FROM AUTHOR]

Carbon Nanotube Field-Effect Transistors (CNFETs) are highly promising to improve the energy efficiency of digital logic circuits. Here, we quantify the Very-Large-Scale Integrated (VLSI) circuit-level energy efficiency of CNFETs versus advanced technology options (ATOs) currently under consideration [e.g., silicon-germanium (SiGe) channels and progressing from today's FinFETs to gate-all-around nanowires/nanosheets]. We use industry-practice physical designs of digital VLSI processor cores in future technology nodes with millions of transistors (including effects from parasitics and interconnect wires) and technology parameters extracted from experimental data. Our analysis shows that CNFETs are projected to offer 9× energy-delay product (EDP) benefit (∼3× faster while simultaneously consuming ∼3× less energy) compared to Si/SiGe FinFET. The ATOs provide <50% EDP benefits. All analyses are performed at the same off-state leakage current density (≤100 nA per micron of FET width) and power density (≤100 W/cm2of chip area). This analysis provides insights into the sources of CNFET EDP benefits and addresses key questions for deeply-scaled technologies. For instance, while contact resistance is a concern for sub-10 nm nodes, CNFETs still provide up to 6.0× EDP benefit (versus Si/SiGe FinFETs) using CNFET contact resistance values already experimentally achieved for 9 nm contact length. [ABSTRACT FROM AUTHOR]

Due to structural disorder effects, variable range hopping (VRH) transport via band-tail states has been widely observed in the transition-metal dichalcogenide field-effect transistor (TMD FET). However, this significant mechanism has not been incorporated into existing compact models. In this letter, a continuous physics-based compact model considering VRH in TMD FET is developed. Key parameters are extracted by calibration to experimental molybdenum disulfide FET. The voltage dependent carrier density and temperature dependent current characteristics are physically predicted by utilizing the general percolation theory and generalized Einstein relation. Our model is validated by the good agreement between the simulation and experimental results. Furthermore, the relationship between the disorder effects and circuit-level performances are presented. This letter is significant for material engineering and device optimization of TMD FET. [ABSTRACT FROM AUTHOR]

FETs made on 2-D semiconductors, typically without degenerate doping at the contacts, have a significant Schottky junction (SJ) resistance, which complicates transistor analysis. This paper evaluates the effect of the contact resistance on the 2-D-material FET characteristics through four-terminal (4-T) resistance measurements on WSe2 FETs, which allow studying the channel and contacts characteristics separately. Apart from showing the nonnegligibility of contact resistance, this paper enables a finer understanding of commonly observed phenomena, such as transistor performance improvement with dielectric-encapsulation is observed to have a stronger effect on the contact than the channel; the resistance of the forward-biased SJ is observed to be not negligible, but comparable to that of the reverse-biased junction; at biases commonly referred to as “low-bias,” the WSe2 FET resistance could be dominated by the contacts; and pinchoff can be observed at relatively lower current levels, being related to the channel-contact resistance ratio rather than their magnitudes. In the devices where true channel pinchoff can be verified, a correlation emerges between current saturating behavior and asymmetry in the output characteristics with respect to the drain–source bias polarity, a feature that may serve as a guide toward interpreting standard FET output characteristics in 2-D materials. [ABSTRACT FROM PUBLISHER]

We have measured the low-frequency 1/ f noise of Si0.55Ge0.45 p MOSFETs with a Si capping layer and SiO2/HfO2/TiN gate stack as a function of frequency, gate voltage, and temperature (100–440 K). The magnitude of the excess drain voltage noise power spectral density ( \textitS {vd} ) is unaffected by negative-bias-temperature stress (NBTS) for temperatures below ~250 K, but increases significantly at higher temperatures. The noise is described well by the Dutta-Horn model before and after NBTS. The noise at higher measuring temperatures is attributed primarily to oxygen-vacancy and hydrogen-related defects in the SiO2 and HfO2 layers. At lower measuring temperatures, the noise also appears to be affected strongly by hydrogen-dopant interactions in the SiGe layer of the device. [ABSTRACT FROM PUBLISHER]

An experimental low-frequency noise (LFN) assessment of long channel Ge pFinFET devices fabricated in different shallow trench isolation (STI) processes is presented, taking into consideration devices with fin widths from 100 nm (planar-like) down to 20 nm. In addition, the correlation among LFN parameters, hole mobility and threshold voltage, is also evaluated. The carrier number fluctuation ( $\Delta N$ ) model is confirmed as dominant mechanism for all studied Ge pFinFETs and there is no correlation with the used STI process. From the LFN, it is evidenced that the Coulomb scattering mobility mechanism plays an important role for STI-first process, resulting in a mobility degradation. [ABSTRACT FROM PUBLISHER]

This paper presents the low-frequency noise (LFN) behavior of vertical tunnel FETs (TFETs). The experimental input characteristics with different source compositions (Si and Ge) and different HfO2 thicknesses in the gate-stack (2 and 3 nm) are presented. A brief analog parameters analysis, including the transconductance, output conductance, and intrinsic voltage gain behavior under different bias conditions, shows that TFETs are promising for analog applications. For the LFN study, the standard number fluctuations model for MOSFETs was used in order to verify and compare the TFETs noise behavior, exploring the influence of different conduction mechanisms in each bias region. In the proposed model, the effective channel length ( L\mathrm{eff} ) is replaced by the tunneling length, resulting in good agreement between the experimental data and the model. The temperature influence on the TFET noise behavior is also investigated. [ABSTRACT FROM AUTHOR]

In this paper, we present an intensive study of 6T-SRAM designs for vertical gate-all-around (GAA) transistors (VFETs) and lateral GAA transistors (LFETs) using 5-nm node design rules. Optimizations of the nanowire (NW) diameter and the gate length are also conducted to enhance the SRAM performance. Device VT retargeting has been proposed for improving the minimum operating voltage ( V\min ) of SRAMs. The isoperformance and isoyield have been performed to assess and determine the benefits provided by LFET and VFET architectures, respectively. Our results show that the VFET bitcells are denser than the LFET bitcells by 20%–30%. The SRAM read stability (read static noise margin) is significantly improved using the NW channel. For a $6\sigma $ yield target and an isoarea of SRAM bitcells, V\min of the VFET bitcell is 80 mV lower than LFET designs. Applying the proposed VT retargeting technique can allow the VFET 122 bitcell to operate at 0.57 V without using assist circuits. A standby leakage below 10 pA/cell can be achieved for both architectures. At isoperformance, the standby leakage of VFET bitcells is $2.6\times $ lower than LFET bitcells. [ABSTRACT FROM AUTHOR]

In this paper, a new scheme called diffusion and gate replacement (D&GR) metal-inserted polysilicon integration is demonstrated. The CMOS flow allows controlling the gate height asymmetry between the nMOS and the pMOS by driving the work function shifter directly into the high- $k$ , and then by removing the dopant source (dummy doped metal gate) and depositing a fresh TiN metal gate. Although the integration flow is compatible with a standard 45-/28-nm technological node, it has been specifically designed to be compatible with dynamic random access memory peripheral applications or other emerging memories (embedded applications). A material down-selection is done (TiN/Mg/TiN gate-stack for nMOS and Al2O3 capping layer for pMOS), and it is demonstrated that a process window exists and guarantees enough work function lowering without compromising the electrical parameters (electrical oxide thickness, mobility, subthreshold slope, and gate leakage). Regarding the CMOS integration, it is shown that an nMOS-first integration is preferable, and that there is no contamination issue of the pMOS work function shifter (in this case, Al2O3) on the nMOS side. Finally, CMOS device performance is on par with the non-D&GR baseline, validating the integration flow. [ABSTRACT FROM AUTHOR]

For sub-7-nm technology nodes, the gate-all-around (GAA) nanowire-based device structure is a strong candidate to sustain scaling according to Moore’s Law. For the first time, the performance of two GAA device options—lateral FET (LFET) and vertical FET (VFET)—is benchmarked and analyzed at the system level using an ARM core processor, based on realistic compact device models at the 5-nm technology node. Tradeoffs among energy, frequency, leakage, and area are evaluated by a multi- Vth optimization flow. A variety of relevant device configurations, including various number of fins, nanowires, and nanowire stacks, are explored. The results demonstrate that an LFET GAA core has a larger maximum frequency than its VFET counterpart because the channel stress that can be created in the LFETs results in a larger ON current. For fast timing targets, the LFET cores are therefore superior. However, for slow timing targets (e.g., 5 ns), the VFET cores with three nanowires offer a 7% area reduction and a 20% energy saving compared with the LFET cores with 2fin/2stack at the same leakage power. [ABSTRACT FROM PUBLISHER]

The gate-stack quality of planar MOSFETs fabricated in Ge-on-Si substrates and passivated by a GeOx interfacial layer is evaluated by low-frequency noise analysis. It is shown that for both n- and p-channel transistors predominantly 1/ f^\gamma noise ( $\gamma \sim 1$ ) has been observed, which originates from number and correlated mobility fluctuations. The oxide trap density and mobility scattering coefficient derived from the input-referred voltage noise power spectral density are demonstrated to be significantly higher for nMOSFETs than for pMOSFETs with the same gate-stack, which explains the low electron mobility. [ABSTRACT FROM PUBLISHER]

In this paper, we compare the performances of FinFETs, lateral gate-all-around (GAA) FETs, and vertical GAAFETs (VFETs) at 7-nm node dimensions and beyond. Comparison is done at ring oscillator level accounting not only for front-end of line devices but also for interconnects. It is demonstrated that FinFETs fail to maintain the performance at scaled dimensions, while VFETs demonstrate good scalability and eventually outperform lateral devices both in speed and power consumption. Lateral GAAFETs show better scalability with respect to FinFETs but still consume 35% more energy per switch than VFETs if made under 5-nm node design rules. [ABSTRACT FROM AUTHOR]

The goal of this paper is to study the analog performance parameters of tunnel field-effect transistors (TFETs) with different source compositions and process conditions. The experimental matrix included devices with either a 100% silicon or Si1–xGex source, so that the germanium amount at the source/channel interface could be correlated with the prevailing transport mechanism and its impact on transconductance (gm), output conductance ( g\mathrm {DS} ), and early voltage ( V\mathrm {EA} ) could be analyzed. The used process conditions were highlighted by comparing a reference split with no Si passivation to the cases with 12 and 18 Si monolayers to determine their influence on the interface trap density and eventual reduction of the traps in the gate oxide. All these process parameters enable to make conclusions on the intrinsic voltage gain ( AV ) and the low-frequency noise. Based on these results, the suitability of each type of TFET has been discussed, revealing that 100% Si may still be considered for analog applications depending on the bias conditions. [ABSTRACT FROM PUBLISHER]

This paper presents a new integration scheme to fabricate a Si/Si0.55~Ge0.45 heterojunction line tunnel field effect transistor (TFET). The device shows an increase in tunneling current with gate length. The 1-\mum gate length device shows on current in excess of 20 \muA/\mum at VGS=VDS=1.2~\rm V. Low-temperature measurements, performed to suppress trap-assisted tunneling (TAT), reveal the point subthreshold swing as low as 22 mV/dec at 78 K. Field-induced quantum confinement effects are found to increase the tunneling onset voltage by \sim0.35~V. Variation of the tunneling onset voltage measured experimentally is correlated to variation in the pocket thickness and its doping concentration. Small geometry devices were found to be more susceptible to microvariations in the pocket thickness and doping concentration. [ABSTRACT FROM AUTHOR]

The role of trap-assisted tunneling (TAT) in the degradation of the subthreshold swing (SS) in n-type line tunnel field-effect transistors (TFETs) is investigated through the experiments and simulations. A two to fourfold increase in the interface state density is achieved by applying a positive or a negative stress between the gate and the source. The negative stress shows no impact on the SS in spite of nearly fourfold increase in the interface state density. A nearly twofold increase in interface state density and improvement in SS are observed under the application of positive stress. The improvement in SS is attributed to H^+ species released from the Si/SiO2 interface during stress, which moves toward the bulk Si, passivating boron and bulk Si traps, thereby improving the SS. Under negative stress bias, the released H^+ species drifts toward the gate electrode, and hence no change in SS was observed. These experiments suggest that the SS degradation is mainly caused by TAT through bulk Si traps and insensitive to interface traps. A good control of bulk semiconductor trap density will be required to achieve sub-60-mV/decade SS in line TFETs. [ABSTRACT FROM PUBLISHER]

In this letter, we present the first InGaAs gate-all-around (GAA) nanowire devices fabricated on 300mm Si substrates. For an \(L_{\mathrm {\mathbf {G}}}\) of 60 nm an extrinsic \(g_{\mathrm {\mathbf {m}}}\) of \(1030~\mu \) S \(/\mu \) m at \(V_{\mathrm {\mathbf {ds}}} = 0.5\) V is achieved which is a \(1.75\times \) increase compared with the replacement fin FinFet process. This improvement is attributed to the elimination of Mg counterdoping in the GAA flow. Ultrascaled nanowires with diameters of 6 nm were demonstrated to show immunity to \(D_{\mathrm {{it}}}\) resulting in an SS \(_{\mathrm {{SAT}}}\) of 66 mV/decade and negligible drain-induced barrier lowering for 85-nm \(L_{\mathrm {{G}}}\) devices. [ABSTRACT FROM AUTHOR]