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This work demonstrates a trench isolated lateral double-implanted MOSFET (LDMOS) on Si-face in 4H-silicon carbide (SiC). A device $\vphantom {_{\int _{}}}$ where ${L}_{\textit {ch}} = 0.8\,\,\mu \text{m}$ and ${L}_{d} = 12\,\,\mu \text{m}$ shows an ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 22.9 $\text{m}\Omega $ cm2 at a ${V}_{\text {GS}}$ of 20 V and a breakdown voltage (BV) of 1100 V, corresponding to a high BV2/ ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 55.5 MW/cm2. Devices that have different ${L}_{\text {ch}}$ , ${L}_{\text {JFET}}$ , ${L}_{d}$ , and P-top dose values are measured in order to investigate the effects of geometry on the static performance. Operations at 150 °C are measured to evaluate the temperature performance. Gate charge waveforms are also measured in order to include the switching performance in the evaluation. The ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{G}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{\text {GD}}$ values are calculated as 17.7 and $9.0~\Omega $ nC, respectively, which are promising for power-integrated circuit applications. [ABSTRACT FROM AUTHOR]

In this letter, the electrical properties of local oxidation of silicon (LOCOS) field oxide formed on 4H-SiC are reported. Moreover, unlike the conventional Si LOCOS process, a simpler method based on Ar preamorphization implantation is proposed. In addition to direct characterization of the field oxide, device properties achieved using LOCOS isolation are compared with those achieved using the conventional chemical vapor deposition oxide isolation to clarify the impact of isolation technology. The results of this letter would be insightful for silicon-carbide-based very-large-scale integration technology. [ABSTRACT FROM PUBLISHER]

Tunnel field-effect transistor (FET) is a promising candidate in ultralow-power applications due to its distinct operation mechanism, namely band-to-band tunneling (BTBT). The integration of different low-bandgap materials is explored extensively to improve the ON-state BTBT current of the tunnel FETs. The epitaxial tunnel layer (ETL) tunnel FET integrated with the hetero-material system is a promising structure due to its process compatibility with CMOS technologies. In the scenario of n-channel operation, the concept of the suppression of the low electric field BTBT is proposed. The SiGe/Si hetero-material system is applied to the n-channel ETL tunnel FET to suppress the low electric field BTBT by the ETL band engineering. The optimized ETL tunnel FET exhibits a high ON-state BTBT current due to the low bandgap material in the ETL. The average SS behavior is also further improved by suppressing the low electric field BTBT. In this study, the design concept and the device parameters of the n-channel ETL tunnel FET are discussed in detail. The performances of the complementary ETL tunnel FETs using the SiGe/Si hetero-material system are also provided to enrich the value of the ETL tunnel FET in the circuit applications. [ABSTRACT FROM PUBLISHER]

The 3-D NAND flash memory architectures will be a future trend, because they provide high memory capacity without aggressively scaling down. A vertical-gate (VG) structure composed of polysilicon (poly-Si) channels is a promising 3-D structure that could facilitate realizing an extremely tight-pitch NAND flash memory cell with high memory capacity. However, the variability of the VG memory cell induced by grain boundaries in the poly-Si channels is a major concern for aggressively scaled-down memory cells. In this paper, a discrete-trap approach is applied to emulate the real trap effects in a 3-D memory cell, and the 3-D structure geometry effects and the variation in the threshold voltage ( VT) induced by the discrete grain-boundary traps are studied. Various \Delta VT behaviors related to the structure geometry and trap position are examined. The effect of varying the body thickness on the \Delta VT is stronger than that of varying the channel width. This paper presents various cases for using the discrete-trap approach to study the variability of VT in 3-D VG memory cells. [ABSTRACT FROM AUTHOR]

The impact of adjacent word-line's pass gate voltage interference on charge-trapping (CT) NAND Flash is extensively studied in this paper. From our previous work with a 38-nm half-pitch BE-SONOS NAND Flash device, we found that the threshold voltage significantly decreases with increasing pass gate voltage during reading. This observation is in contrary to the common belief that the CT NAND devices are immune to interference. In this paper, we further evaluate the pass gate voltage interference on 3-D CT NAND Flash, which is the most promising path for the future NAND Flash industry. Owing to the superior gate control ability in the double-gate architecture, the commonly observed pass gate voltage interference due to pitch scaling is suppressed. Stronger gate control ability also restrains the impact of field penetration in devices with narrow channel width. In 3-D CT NAND Flash, the thinner channel can also provide better gate control ability, which, in turn, results in smaller pass gate voltage interference. [ABSTRACT FROM PUBLISHER]

The 3-D stacking of multiple layers of NAND using thin-film transistor (TFT) devices is widely accepted as the next step in continuing NAND Flash scaling. Low mobility and reliability problems are two well-known concerns regarding TFT devices. However, another important implication of using TFT devices is that the Vt variation induced by randomly distributed grain boundaries degrades the array performance. In this paper, an extensive TCAD simulation was conducted to systematically investigate how grain boundary generated traps affect NAND Flash devices. Minimizing the density of grain boundary traps is crucial for array performance. In addition, optimal gate control ability reduces the impact of grain boundaries. Thus, using double gate architecture in vertical gate 3-D NAND is favorable. Furthermore, when pitch is scaled in the future, device exhibiting smaller channel thickness should be used to increase the gate control. [ABSTRACT FROM PUBLISHER]

The tunnel field-effect transistor (FET) is a promising candidate for use in ultralow-power applications because of its distinct operation principle, namely, band to band tunneling (BTBT). However, the ON-state current of the tunnel device is extremely low because of the poor tunneling efficiency of the BTBT. In this paper, a novel epitaxial tunnel layer (ETL) structure combining vertical tunneling orientation was proposed. The ETL structure performs more favorably than does the traditional lateral tunnel FET structure in an all-silicon device. By using low bandgap materials in the ETL, the ON-state BTBT current increases and an extremely low intrinsic OFF-state current is maintained because of the small low bandgap junction area. The onset voltage of the bipolar BTBT can also be postponed using ETL band engineering. The optimized parameters of the Six\rm Ge1\-{\rm x} ETL tunnel FET structure increase the ON-state current 10^7\--10^8 times compared with that of the traditional lateral silicon tunnel FET. The minimal subthreshold swing (SS) and ON/OFF current ratio also improve, the SS decreases from 47 mV/decade to 29 mV/decade, and the ON/OFF current ratio increase from 10^5 to 10^10. In this paper, the effects of the ETL parameters on device performance are discussed in detail. [ABSTRACT FROM PUBLISHER]

The gate-to-source capacitance ( C\mathrm {GS}) in the p-channel tunnel FET (pTFET) with a Ge epitaxial tunnel layer (ETL) structure is investigated. The characteristic of C\mathrm {GS} is revealed and studied with various frequencies and temperatures. Due to the highly efficient band-to-band tunneling (BTBT) in the Ge ETL pTFET, the minority carriers for the source can be generated by the BTBT process and can respond with the gate voltage. Therefore, the contribution of C\mathrm {GS} to the total gate capacitance in the ON-state would increase, which results in a decrease of the gate-to-drain capacitance. This property is beneficial to the suppression of the Miller capacitance effect on the TFET-based circuit. [ABSTRACT FROM AUTHOR]

A CMOS process compatible p-channel tunnel field-effect transistor (TFET) with an epitaxial tunnel layer (ETL) structure is demonstrated experimentally. The fabricated ETL p-TFET exhibits high tunneling current ( I\mathrm{\scriptscriptstyle ON}\sim 0.17~\mu \text{A}/\mu \text{m} at \vert VG\vert =0.5 V after V\mathrm {TH} adjustment), ultra-low OFF-state current, and good average subthreshold swing (S.S. $\sim 100$ mV/ decade up to 10 nA/ \mu \text{m} ). Overall performance exceeds that of the current state-of-the-art Ge-based planar p-TFETs. [ABSTRACT FROM AUTHOR]

Lower saturation current flowing through the same cell twice is a major drawback of vertical stack array transistor architecture. A loading effect further reduces the saturation current and causes higher threshold voltage. A simple word line cut process not only doubles the bit density to reduce the bit cost, but also reduces the loading effect. This letter used an assisted gate can to further enhance the saturation current with acceptable cell characteristics. Furthermore, the major parameters that influence the performance of the vertical stack array transistor architecture were studied extensively. An ultra-high density three-dimensional NAND flash architecture can be used in the future NAND flash industry. [ABSTRACT FROM PUBLISHER]

Extreme ultraviolet (EUV) irradiation may induce damages on high-dielectric-constant (high- k) dielectrics. In this letter, the EUV-irradiation-induced damages on HfSiO, HfAlO, and \Al2\O3 are investigated. After EUV irradiation, hole traps, border traps, and interface traps are all increased. All of the three high-k dielectrics exhibit poorer immunity to the EUV irradiation than \SiO2. The oxide traps scale down with the dielectric thickness. Interfacial layer plays an important role in the increase of border traps and interface traps. Therefore, high-quality SiO-like interfacial layer is critical for radiation-hard devices. [ABSTRACT FROM PUBLISHER]

The effects of extreme-ultraviolet (EUV)-irradiation-induced damage on the characteristics of a silicon–oxide–nitride–oxide–silicon (SONOS) memory device are investigated. After EUV irradiation, changes in the memory window and program/erase speed indicate the generation of positive charges and new traps. Retention performance degrades after high-dose irradiation, which indicates that the tunneling layer is damaged. Endurance performance degrades severely because the damage in the blocking oxide results in serious electron back injection after cycling operations. These defects cannot be recovered after 600 ^\circ\C annealing. It is recommended that in-process high-dose EUV irradiation on a SONOS stack after a front-end-of-line process should be avoided. [ABSTRACT FROM AUTHOR]

High-performance polycrystalline-silicon (poly-Si) nanowire (NW) thin-film transistors (TFTs) using hafnium dioxide (\HfO2) as gate dielectric is successfully fabricated for the first time. The excellent short-channel characteristics are attributed to the high- \kappa gate dielectric, ultrathin poly-Si NW channel thickness, and omega-shaped gate structure. The record high driving capability of 549 \mu \A/\mu\m results from the ultrashort gate length (LG), thin equivalent oxide thickness, and Ni silicide metal source/drain. This letter reveals the opportunity of high-performance poly-Si TFT circuits for system-on-panel and 3-D integrated circuit (3-D IC) applications. [ABSTRACT FROM PUBLISHER]