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Summary: In this paper, a low‐power transconductor‐capacitor (Gm‐C) filter with programmable cutoff frequency is designed for electroencephalogram (EEG), electrocardiogram (ECG), and surface electromyography (sEMG) biosignals. The second‐order Butterworth low pass filter (LPF) is designed as an interface between an instrumentation amplifier (IA) and an analog‐to‐digital converter (ADC). The proposed Gm‐C filter suppresses out‐of‐band components and also plays an anti‐aliasing role. With the variable transconductance based on flipped voltage follower (FVF), the cutoff frequencies of 100 Hz, 560 Hz, and 1.5 kHz are obtained for EEG, ECG, and sEMG, respectively. This structure is highly accurate by using a robust and low‐power common mode feedback (CMFB). With 0.8 V supply voltage, the total power consumption of the filter is only 56 nW, 100 nW, and 221 nW for cutoff frequencies of 100 Hz, 560 Hz, and 1.5 kHz, respectively. The proposed Gm‐C filter is simulated in TSMC 65 nm CMOS technology and occupies an area of 0.12 mm2. The figure of merit (FOM) of the proposed filter is equal to 1.9 pW/pole. [ABSTRACT FROM AUTHOR]

In this paper, a low‐noise amplifier (LNA) with process, voltage, and temperature (PVT) compensation for low power dissipation applications is designed. When supply voltage and LNA bias are close to the subthreshold, voltage has significant impact on power reduction. At this voltage level, the gain is reduced and various circuit parameters become highly sensitive to PVT variations. In the proposed LNA circuit, in order to enhance efficiency at low supply voltage, the cascade technique with gm boosting is used. To improve circuit performance when in the subthreshold area, the forward body bias technique is used. Also, a new PVT compensator is suggested to reduce sensitivity of different circuit's parameters to PVT changes. The suggested PVT compensator employs a current reference circuit with constant output regarding temperature and voltage variations. This circuit produces a constant current by subtracting two proportional to absolute temperature currents. At a supply voltage of 0.35 V, the total power consumption is 585 μW. In different process corners, in the proposed LNA with PVT compensator, gain and noise figure (NF) variations are reduced 10.3 and 4.6 times, respectively, compared to a conventional LNA with constant bias. With a 20% deviation in the supply voltage, the gain and noise NF variations decrease 6.5 and 34 times, respectively. [ABSTRACT FROM AUTHOR]

In this paper, two low phase noise and power consumption VCO circuits, which are suitable for Internet of things (IoT) applications, are proposed. In the first structure, in order to have more control of the current consumption, the current shaping technique is used in the PMOS and NMOS biasing circuit. In the second structure, for increasing the oscillation amplitude and reducing the phase noise, independent biasing for the NMOS section is used. In both structures, to increase the frequency tuning range (FTR), without using a capacitor bank, the varactor is used in the biasing structure. In the first structure the supply voltage, output frequency, power consumption, and phase noise are 0.8 V, 2.44 GHz, 0.37 mW, and -117.5 dBc/Hz, respectively, but in the second structure, the supply voltage, output frequency, power consumption, and phase noise are 0.8 V, 2.44 GHz, 0.62 mW, and -120 dBc/Hz, respectively. It should be noted that the two structures are designed and simulated in 65-nm CMOS technology. Finally, the results show that the figure-of-merit for the first and second structures is -190 dBc/Hz and -190.2 dBc/Hz, respectively. [ABSTRACT FROM AUTHOR]

In this paper a DC-DC converter with high voltage conversion ratio and low chip area, which is useful for RFID tag chip, is presented. DC-DC converter is modeled with neural network while TLBO algorithm is used to optimize it. In each stage of the converter the charge transfer switch is used for increasing the voltage gain. Each charge transfer switch is dynamically controlled with the inverter and the charge transfer switch is completely becomes on and off. By using the achieved results of the TLBO algorithm, the output voltage and voltage conversion ratio of DC-DC converter are 7.741V and 86%, respectively, while the input voltage is considered 1.8V. The layout of the DC-DC converter chip area drawn in Cadence software is 60 µm*60µm. The neural network and TLBO algorithm are programed with Matlab software and the Cadence software is used for extracting the circuit primary samples and simulating the final design of DC-DC converter in 0.18 µm CMOS technology. [ABSTRACT FROM AUTHOR]

In this paper, a robust 12T-SRAM memory cell at sub-threshold voltage is designed to reduce power consumption for low power applications, that in addition to reducing power consumption can perform well at high frequencies and remain stable. For the write operation, a new method has been used that removes the write bit line and uses the supply voltage in each cell for this operation and only by applying control signals. Also, the embedded bit line is used only for read operations and reduces the activity of the bit line, and due to being floating and the way of writing, eliminates the Precharge and Write Driver circuits, so, part of the power and area consumption has been reduced. According to the techniques used, the write and read noise margin is significantly improved and the write operation become easier to perform. Also due to the existence of a separate path for the read operation, RSNM is equaled to the HSNM. The average cell power at the frequency of 100 MHz for low power applications and 0.2V supply voltage, as compared to the best previous designs, has been improved by 34.9% and the leakage power of the hold state has been reduced by 27.6% and PDP has been improved by more than 35.2%, further, the maximum operating frequency of the cell has been increased by 39.1%, while it operates with the sub-threshold voltage of 0.2V to the frequency of 2.173 GHz. [ABSTRACT FROM AUTHOR]

In this paper, a new compensation technique for the low noise amplifier (LNA) with the high capability and efficiency for low power applications is proposed. The supply voltage and bias of the LNA are near the sub-threshold voltage, which has excellent effect on reducing power consumption. At this voltage level, the gain decreases and the various circuit parameters become extremely sensitive to process, voltage and temperature (PVT) changes. To overcome the problem, a compensating circuit with variable current source to control the LNA bias voltage is used. The output of the compensator circuit is adjusted according to changes in temperature, voltage and five process corners, and produces a variable voltage. The temperature compensator consists of two current sources that produce a current proportional to temperature changes. Regarding process and voltage compensator, according to the state created in the circuit, the appropriate amount of current is injected through the output and finally stabilizes the main parameters of the LNA circuit. In LNA circuit, for proper performance at supply voltage near the sub-threshold and attaining the gain improvement, forward body bias and g m -boosting techniques are employed, respectively. The LNA circuit along with the PVT compensator at supply voltage of 0.35 V, consumes about 567 µW power consumption that here 91 µW is caused by the PVT compensator circuit. In the proposed circuit, the rate of noise figure (NF) and gain (S 21) changes compared to temperature changes in the five corners have decreased by 4.3 and 12.1 times versus LNA with constant bias, respectively. In this case, with 20% changes of V DD , NF and S 21 changes decreased by 23 and 11.35 times, respectively. The results are provided by Cadence software using 65 nm CMOS technology. [ABSTRACT FROM AUTHOR]

this brief presents a new 11-bit 1.2 ​GS/s hybrid digital to analog converter (DAC) simulated in 65 ​nm CMOS technology. In this new structure, a combination of a resistor ladder and current sources is used to realize the 11-bit DAC structure. The current sources are connected to different nodes of the resistor ladder in a logical way. In this situation, equal current sources make different voltage values. Furthermore, the complicated binary to thermometer decoders are exchanged with the basic digital logics. This new technique remarkably reduces the number of current sources needed for realization an 11-bit DAC and leads to the circuit dissipates just 4.68 ​mW power while the power supply is 1.2 ​V. Also, the occupied area is 0.0061 ​mm2. Post layout simulation results indicate that the spurious-free dynamic range (SFDR) is more than 70 ​dB over 600 ​MHz Nyquist BW. The INL and DNL parameters are also obtained better than 1.2 LSB and 1 LSB, respectively. [ABSTRACT FROM AUTHOR]