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Digital Signage can be quickly updated, greatly enhancing functionality compared to traditional paper signs. Worries about climate change, carbon footprint, energy shortages and light pollution means Signage should be low power with low light pollution. In response, E Ink has developed Kaleido reflective ePaper outdoor displays with good color performance. On a spectrum between paper signs and other forms of full color electronic display Kaleido is much closer to paper signs in power use and lighting impact. Operating temperature range is ‐15°C to 65°C, removing the need for expensive, power hungry heating and cooling. [ABSTRACT FROM AUTHOR]

There has been much interest in replacing traditional information supports with more technological solutions in recent years. New technologies which allow paper-like perception with minimal power needs have emerged as low-power wireless scenarios. A priority for these new supports is to create the architecture for a scalable solution which maintains minimal power requirements. The retail industry demands a new information infrastructure that improves customer and employee satisfaction. In this work, authors propose an information provision architecture based on E-Paper and carry out an experiment where different smart labeling architectures based on Paper, E-Paper, LED liquid crystal display (LCD) and Dot-matrix LCD were tested in order to determine which is best suited for a real labeling environment. Enclosed in a research project called SMARKET, the authors pilot-tested the work in a real supermarket, having the opportunity to survey employees and customers about satisfaction and frustration with the use of the architectures proposed in this research work. [ABSTRACT FROM AUTHOR]

This paper presents a shock detection device for packages in the supply chain. The primary purpose is to identify package damage during storage, delivery, and handling. Additionally, products are likely to be damaged if dropped from a certain height, which sometimes does not appear on the package. By continuously measuring package vibrations and detecting shocks in the supply chain, consumers can gain an insight into the state of the product upon delivery. This paper presents the Smart Sticker implementation for ultra-low-power shock detection in the supply chain. The overall energy consumption must be kept as low as possible while continuously sensing the presence of shock to ensure that the Smart Sticker's battery lasts as long as possible. The Smart Sticker functions in three modes to meet the established constraints: low-power, active, and data transfer mode. While detecting the shock, the low-power mode uses the least amount of energy needed. If the shock exceeds the threshold, the Smart Sticker enters active mode, stores the detected g force value in memory, and then switches back to low-power mode. Finally, employing Near Field Communication (NFC) and energy harvesting, the data transfer mode allows the consumer to read the recorded data. The results show that the Smart Sticker for shock detection performs according to set requirements and successfully monitors and detects shock for packages in the supply chain. [ABSTRACT FROM AUTHOR]

High‐transmission, high contrast ratio and low‐power‐consumption amplified intrinsic fringe field (AIFF) multi‐domain vertical alignment (MVA) LCD's are developed for microdisplay for augmented reality, portable smart phones, GPS, tablet, and LC TV display applications. The AIFF MVA design eliminates all protrusions and ITO slits in TFT and CF.substrates, resulting in high transmission and high yield. The no‐pretilt fabrication process is low cost, does not require PI rubbing and special photoalignment process, and uses standard IC, LC, and PI materials. AIFF MVA is the only LCD mode without edge disclinations. It is compatible with the RGBW square pixel designs for low power consumption LCD applications. [ABSTRACT FROM AUTHOR]

In this paper, a new structure for a 1-bit full adder is proposed based on dynamic logic methodology, which utilises pass transistors. The clocking operation falls into two phases. The clocking operation consists of a pre-discharged cycle, during which pseudo capacitors are reset to zero when the clock signal is high, and an evaluation cycle, during which the circuit outputs the adder function when the clock signal is low. The circuit uses a combination of 12 pass-transistors to better implement the full adder logic function with the maximum of a NMOS threshold voltage drop. Moreover, the circuit has no direct connection to the power-supply node and so this can possibly save the power dissipation. Our new adder outperforms other 1-bit full adder structures in terms of power-delay factor, according to simulation results. [ABSTRACT FROM AUTHOR]

The Internet of Things (IoT) and blockchain are emerging technologies that have attracted attention in many industries, including healthcare, automotive, and supply chain. IoT networks and devices are typically low-powered and susceptible to cyber intrusions. However, blockchains hold considerable potential for securing low-power IoT networks. Blockchain networks provide security features such as encryption, decentralisation, time stamps, and ledger functions. The integration of blockchain and IoT technologies may address many of the security concerns. However, integrating blockchain with IoT raises several issues, including the security vulnerabilities and anomalies of blockchain-based IoT networks. In this paper, we report on our experiments using our blockchain test bed to demonstrate that blockchains on IoT platforms are vulnerable to DDoS attacks, which can also potentially lead to device hardware failures. We show that a number of anomalies are visible during either a DDoS attack or IoT device failure. In particular, the temperature of IoT hardware devices can exceed 90 °C during a DDoS attack, which could lead to hardware failure and potential fire hazards. We also found that the Block Transaction Rate (BTR) and network block loss percentage can increase due to corrupted hardware, with the BTR dropping to nearly zero blocks/sec and a block loss percentage of over 50 percent for all evaluated blockchains, and as high as 81.3 percent in one case. Our experiments demonstrate that anomalous temperature, latency, bandwidth, BTR, and network block loss percentage can potentially be used to identify DDoS attacks. [ABSTRACT FROM AUTHOR]

Edge computing enables prompt responses in IoT environments, such as the operation of autonomous vehicles and unmanned aerial vehicles. However, with the increase in sensor nodes, the computational burden on the computing node also increases. Specifically, data filtering and reduction at application nodes add to the energy burden for battery-operated devices. In this paper, we propose a preprocessing system at the application node that requires low power consumption for data transmission reduction. Based on our simulations, we identify the minimum data size needed to preserve the signal. We first design the preprocessing system using a hardware description language to evaluate its performance. Then, we implement the open-library-based MCU system, including the proposed preprocessing IP, to assess its operation and overhead. Our implementation of the preprocessing system reduces data transmission by 50% with acceptable information loss. Additionally, the area and power consumption after the logic synthesis of the preprocessing IP within the entire MCU system are evaluated at only 3.6% and 13.1%, respectively. By performing preprocessing using the MCU and proposed IP, nearly 74.4% power reduction is achieved compared to using the existing MCU core. [ABSTRACT FROM AUTHOR]

Brain-inspired flexible neuromorphic devices are of great significance for next-generation high-efficiency wearable sensing and computing systems. In this paper, we propose a flexible organic electrochemical transistor using poly[(bithiophene)-alternate-(2,5-di(2-octyldodecyl)- 3,6-di(thienyl)-pyrrolyl pyrrolidone)] (DPPT-TT) as the organic semiconductor and poly(methyl methacrylate) (PMMA)/LiClO4 solid-state electrolyte as the gate dielectric layer. Under gate voltage modulation, an electric double layer (EDL) forms between the dielectric layer and the channel, allowing the device to operate at low voltages. Furthermore, by leveraging the double layer effect and electrochemical doping within the device, we successfully mimic various synaptic behaviors, including excitatory post-synaptic currents (EPSC), paired-pulse facilitation (PPF), high-pass filtering characteristics, transitions from short-term plasticity (STP) to long-term plasticity (LTP), and demonstrate its image recognition and storage capabilities in a 3 × 3 array. Importantly, the device's electrical performance remains stable even after bending, achieving ultra-low-power consumption of 2.08 fJ per synaptic event at −0.001 V. This research may contribute to the development of ultra-low-power neuromorphic computing, biomimetic robotics, and artificial intelligence. [ABSTRACT FROM AUTHOR]

Bluetooth Low Energy Mesh (BLE Mesh) enables Bluetooth flexibility and coverage by introducing Low-Power Nodes (LPNs) and enhanced networking protocol. It is also a commonly used communication method in sensor networks. In BLE Mesh, LPNs are periodically woken to exchange messages in a stop-and-wait way, where the tradeoff between energy and efficiency is a hard problem. Related works have reduced the energy consumption of LPNs mainly in the direction of changing the bearer layer, improving time synchronization and broadcast channel utilization. These algorithms improve communication efficiency; however, they cause energy loss, especially for the LPNs. In this paper, we propose a constrained flooding algorithm based on time series prediction and lightweight GBN (Go-Back-N). On the one hand, the wake-up cycle of the LPNs is determined by the time series prediction of the surrounding load. On the other, LPNs exchange messages through lightweight GBN, which improves the window and ACK mechanisms. Simulation results validate the effectiveness of the Time series Prediction and LlightWeight GBN (TP-LW) algorithm in energy consumption and throughput. Compared with the original algorithm of BLE Mesh, when fewer packets are transmitted, the throughput is increased by 214.71%, and the energy consumption is reduced by 65.14%. [ABSTRACT FROM AUTHOR]

Although CNN shows high performance in the image recognition field, it has great disadvantages. They are to take a long time to perform machine learning due to a lack of system resources, and to consume a lot of power due to the great volume of computation. A convolution layer is a key element of convolutional neural network processing. This paper presents a convolution layer hardware using processing elements with a low-power multiplier. The low-power multiplier reduces the switching activity by increasing the exchange rate between the multiplier and multiplicand. The proposed convolution layer hardware was implemented on the Intel DE1-SoC FPGA Board using Verilog-HDL. The performance was verified by comparing the exchange rate with the existing multipliers when performing multiplications to process convolutional operations for the MNIST image database. [ABSTRACT FROM AUTHOR]

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Modern processors often face challenges when handling instructions that overwhelm the branch target buffer (BTB), leading to front-end bottlenecks. As the BTB's capacity increases, its prediction module can become slower and power-hungry. In this paper, we introduce a straightforward yet highly effective two-level prediction mechanism to mitigate the escalating power consumption in the BTB structure, achieved by reducing the number of accesses. Our approach incorporates two main elements: M-BTB and V-BTB. M-BTB encompasses the first-level prediction mechanism and a fully associative BTB, while V-BTB houses the second-level prediction mechanism and a set-associative BTB. To implement our prediction mechanism, we optimize the traditional two-level BTB structure. The first level employs the skew mechanism, and the second level dissects the tag bits to create the Partial tag. These two levels of prediction mechanism correspond to the bank/way prediction for the two-level BTB structure. Our experimental results show that the first-stage prediction mechanism reduces M-BTB accesses by 75%, while the second-stage prediction mechanism ensures that over 98% of addresses require just zero or one way of the V-BTB to achieve a hit result. Our proposed approach achieves a remarkable 86–97% reduction in power consumption, with a minimal impact on performance and an increase in overall area efficiency. [ABSTRACT FROM AUTHOR]

The constant growth of social media, unconventional web technologies, mobile applications, and Internet of Things (IoT) devices create challenges for cloud data systems in order to support huge datasets and very high request rates. NoSQL databases, such as Cassandra and HBase, and relational SQL databases with replication, such as Citus/PostgreSQL, have been used to increase horizontal scalability and high availability of data store systems. In this paper, we evaluated three distributed databases on a low-power low-cost cluster of commodity Single-Board Computers (SBC): relational Citus/PostgreSQL and NoSQL databases Cassandra and HBase. The cluster has 15 Raspberry Pi 3 nodes with Docker Swarm orchestration tool for service deployment and ingress load balancing over SBCs. We believe that a low-cost SBC cluster can support cloud serving goals such as scale-out, elasticity, and high availability. Experimental results clearly demonstrated that there is a trade-off between performance and replication, which provides availability and partition tolerance. Besides, both properties are essential in the context of distributed systems with low-power boards. Cassandra attained better results with its consistency levels specified by the client. Both Citus and HBase enable consistency but it penalizes performance as the number of replicas increases. [ABSTRACT FROM AUTHOR]

Digital Image Processing has dominated Digital Signal Processing at the cost of more memory, resources, and high computational power. In image processing, filtering transformations and other operations need complex multiplications, and the multiplier is one of the most resources consuming elements. Recently, mitigating the multiplier complexity in the digital signal processing (DSP) algorithms sigma-delta modulation based general purpose and adaptive DSP algorithms are developed in MATLAB and compared with its counterpart multibit algorithms for functionality and area-performance-power in FPGA. The contemporary multiplier algorithms are also optimized to overcome the multiplier complexity challenge as computation becomes simple and fast. This paper extends the reported work by investigating the sigma-delta modulation approaches for developing a computationally efficient low-power image processing algorithm. The proposed model is designed, developed, and simulated in MATLAB. The simulation results are analyzed using SNR, MSE, and Peak SNR. The simulation results show that the proposed system can better mitigate the noise effect, making it robust for noisy environment. [ABSTRACT FROM AUTHOR]

This paper presents a CNFET (Carbon Nano-tube FET) based MT (Multi-Threshold)-SRAM (Static Random Access Memory) design based on the leakage reduction mechanism. A multi-threshold logic is employed for reducing the leakage current during read/write operations. Here, the multi-threshold technique is used to insert the high threshold sleep control to the low threshold circuit. The insertion is performed in a serial manner. The high threshold transistors are very useful for deriving the low sub-threshold current. Meanwhile, the low threshold transistors are promising for improving the circuit performance. The high-low threshold transistor pairs are used to change the channel length by modifying the oxide thickness of the transistors. The overall implementation of the Multi-threshold-based SRAM cells are implemented with the help of CNFET in-order to avoid the short channel effect, mobility degradation which is occurred while considering the channel length below 32 nm in CMOS (Complementary Metal Oxide Semiconductor) devices. The paper clearly represents the performance improvement of the proposed SRAM cells with above-mentioned technologies. [ABSTRACT FROM AUTHOR]

This paper presents a class of zero-power microwave sensor architecture based on the direct-conversion principle to eliminate data processing at the Internet of Things sensors and provide unpowered nodes. A base station (BS) transmits a single tone signal at the frequency of $f_{0}$ /2 toward the sensing node using an antenna. At the node, an antenna receives the signal, and a passive frequency doubler makes the frequency twice. Then, a multi-port structure directly modulates the sensing data at the frequency of $f_{0}$ and sent back to the BS by an antenna. The multi-port circuit has one input, one output, and some loading ports. In this paper, a six-port modulator and four similar sensitive capacitive resonators are used. A pair of resonators senses the variation of a sample under test (SUT) while the other pair is covered by a reference or known material. At the BS, any quadrature receiver can be used to demodulate sensing data. Here, a similar six-port structure is used to extract data and find the SUT variations. An example one-node system is implemented at $f_{0} = 2.45$ GHz and evaluated by some standard SUTs. To support multiple nodes, a smart directional antenna is necessary at the BS, which also improves the overall efficiency of the system. [ABSTRACT FROM AUTHOR]

The survival rate for sudden cardiac arrest (SCA) is low, and patients with long-term risks of SCA are not adequately alerted. Understanding SCA's characteristics will be key to developing preventive strategies. Many lives could be saved if SCA's early onset could be detected or predicted. Monitoring heart signals continuously is essential for diagnosing sporadic cardiac dysfunction. An electrocardiogram (ECG) can be used to continuously monitor heart function without having to go to the hospital. A zeolite-based dry electrode can provide safe on-skin ECG acquisition while the subject is out-of-hospital and facilitate long-term monitoring. To the ECG signal, a low-power 1 μW read-out circuit was designed and implemented in our prior work. However, having long-term ECG monitoring outside the hospital, i.e., high battery life, and low power consumption while transmission and reception of ECG signal are crucial. This paper proposes a prototype with a 10-bit resolution ADC and nRF24L01 transceivers placed 5 m apart. The system uses the 2.4 GHz worldwide ISM frequency band with GFSK modulation to wirelessly transmit digitized ECG bits at 250 kbps data rate to a physician's computer (or similar) for continuous monitoring of ECG signals; the power consumption is only 11.2 mW and 4.62 mW during transmission and reception, respectively, with a low bit error rate of ≤0.1%. Additionally, a subject-wise cross-validated, three-fold, optimized convolutional neural network (CNN) model using the Physionet-SCA dataset was implemented on NVIDIA Jetson to identify the irregular heartbeats yielding an accuracy of 89% with a run time of 5.31 s. Normal beat classification has an F1 score of 0.94 and a ROC score of 0.886. Thus, this paper integrates the ECG acquisition and processing unit with low-power wireless transmission and CNN model to detect irregular heartbeats. [ABSTRACT FROM AUTHOR]

This paper presents a single-ended 11T sub-threshold SRAM (SE11T) based on 10-nm FinFET technology. The performance of the proposed design is evaluated and compared with those of other state-of-the-art SRAMs namely 6T, 8T, DIRP10T, ST2, PPN10T, and FC11T at VDD = 0.3 V. The proposed design improves read stability by 2.08X/1.31X/1.03X compared to 6T/ST2/PPN10T due to the read-decoupling technique. Furthermore, it improves writability by 1.42X/2.85X/1.35X/1.28X compared to 6T/DIRP10T/ST2/PPN10T owing to feedback-cutting scheme. The use of write bitline free structure make the proposed SRAM consumes at least 2.79X lower dynamic power. The static power is reduced in the proposed SRAM by at least 1.09X. The reduction is because of the stacking of the transistors, the long path from power VDD to ground, and eliminated leakage in read path. The proposed SRAM works reliably even when exposed to extreme process variations. The proposed bitcell occupies a 1.46X/1.19X higher area than that of 6T/8T. The proposed design improves most of the design metrics and can be an efficient candidate for portable applications with budgeted power. [ABSTRACT FROM AUTHOR]

An artificial intelligence of things (AIoT) chip is a critical hardware component in edge devices that supports data acquisition and processing in the artificial intelligence (AI) era. In this paper, we introduce the architecture and circuit techniques for AIoT systems as well as the design challenges associated with them. To address the design challenges, we describe our design approaches to improve energy efficiency from the standpoints of system architecture, AI computing, and data acquisition circuits. Meanwhile, we present our most recent research progress and state-of-the-art AIoT chip demonstrations at a prestigious conference. Our design techniques improve power and energy efficiency by orders of magnitude on corresponding state of the arts (SOTA), allowing for an advanced AIoT chip design. [ABSTRACT FROM AUTHOR]

In this paper, we present an analysis of an operational trans-conductance amplifier (OTA) with two positive feedback. The direct current (DC) transfer function is obtained by analyzing the OTA using the drain current in the weak inversion region. The analysis results were verified through comparison with SPICE simulations, and the characteristics of the DC transfer function analysis for the OTA design are well matched with the simulation results. The designed OTA dissipates a low power of 41.4 nW, and features the slew rate is improved by 436% compared to a conventional OTA without two positive feedback. Additionally, a DC gain and a unity-gain bandwidth is improved by 36 dB and 6.7 times, respectively. The OTAs are designed for the 0.18 µm complementary metal-oxide-semiconductor (CMOS) process. [ABSTRACT FROM AUTHOR]

This paper proposes a novel analog front end to filter edges in captured images. The proposed architecture employs the Sobel algorithm and uses a 3 × 3 kernel to process the input images. We used 180 nm Semi-Conductor Laboratory (SCL) CMOS fabrication technology for implementation with a power supply of 1.8 V. The proposed design employs six analog differential pairs in each horizontal and vertical gradient unit. The inputs to the differential pairs are the active signals fed from the 3 × 3 kernel using the Sobel weight masks. We connected the differential datum pairs in cascade to estimate the gradient index in horizontal/vertical direction using the net difference current between the output terminals. The horizontal and vertical gradient units, viz., G H and G V , respectively, are configured based on the polarity of weights in respective Sobel masks. The gradient (G) of the processing pixel (PP) is estimated using the net difference current in the combined circuitry employing G H and G V cells. The key advantages of the proposed design are very low area realization, high accuracy, and low power dissipation. The efficacy of the proposed edge filter analog front end is estimated through simulations and analysis with two sets of test signals in the processing window. [ABSTRACT FROM AUTHOR]

Currently, static circuit power is becoming a major concern, dominating the total power consumption due to the scaling down of CMOS technology. The smaller sizes drastically affect the leakage current, which integrated circuit designers attempt to overcome this issue. Hence, several methods and technologies have been proposed to prevail this phenomenon. One of these methods is using memory structures in logic designs. A Hybrid MTJ/CMOS circuit is one of these promising techniques to design low-power nonvolatile circuits with power gating ability and low overhead for reconfigurable possibilities. In this paper, we have proposed a fully nonvolatile, low-power Full-Adder based on MTJs that uses the spin transfer torque method assisted by the spin hall effect. Simulation results of these designs by HSPICE show that they can work fast with low-power consumption compared to other state-of-the-art nonvolatile full-adders. [ABSTRACT FROM AUTHOR]

Wireless Body Area Network (WBAN) is a wireless network of short-range communication protocols for remote healthcare monitoring with the possibility of giving freedom of human body movements. Sensor nodes (motes) are usually located under the skin, implanted deep in the body, or ingested, as in the rare case of smart pills for medical and non-medical usage. Since the necessary connections of wearable and implantable devices are wireless, and the components use low batteries, processing and transferring the critical data can deplete the nodes' power. In most cases, it is impossible to exchange or re-power batteries. Holter monitoring, loop recorders, and wireless capsule endoscopy are some of the WBAN's applications for saving and transferring medical data. Wireless capsule endoscopy is the application for image transmission in WBANs, and the image compression in common is a specific segment of capsule endoscopy. Since the better compression of images increases the frame rate and typically improves the diagnosis process, selecting the compression algorithm should be relevant. The considerable scope of this comprehensive study pays attention to the various biomedical data compression approaches in WBANs. This paper focuses on power-efficient schemes of remote healthcare networks. In this survey article, the energy-based biomedical data compression approaches of WBANs and remote healthcare networks are accurately classified based on lossy, lossless, and hybrid techniques; later, a comprehensive comparison of each specific method's power consumption is presented. [ABSTRACT FROM AUTHOR]

With the emerging of Internet of Things (IoT) industry, applications like smart power plugs, security ID tags, home automation and wearable electronic devices all make the demand for low-power WiFi chips impendency. In this paper, a low-power 2.4 GHz 802.11b/g/n WiFi system-on-chip (SoC) is designed and implemented with 40-nm CMOS process, with area of 8.1 mm2. The low-power SoC integrates 32-bit microcontroller, 802.11b/g/n WiFi baseband, 2.4 GHz RF transceiver, ample memory space, ADC, 6-channel PWM, flexible I/O interfaces, multi-stage power management module, etc. It has several sleep modes with extremely low leakage current as 0.8 mA/12 µA in light/deep sleep mode and 0.4 µA in shutdown mode to reduce the power consumption. High performance is demonstrated, including Pout (−28 dB/-30 dB EVM) of 20.1 dBm/19.1 dBm and RX sensitivity of −76 dBm/-74 dBm meanwhile the total current of 148.5 mA/146.5 mA (TX) for 54 Mbps OFDM/HT20 MCS7. [ABSTRACT FROM AUTHOR]