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We have fabricated and tested the performance of sub-50nm gate nMOSFETs to assess their suitability for mixed signal applications in the super high frequency (SHF) band, i.e. 3-30GHz. For a 30nm×40 μm×2 device, we found f(T) =465GHz at V(ds)=2V, V(g)=0.67V, which is the highest cut-off frequency reported for a MOSFET produced on bulk silicon substrate so far. However, our measurements of f(max) and noise figure indicate that parasitics impose limitations on SHF operation. We also present a high-frequency ac model appropriate to sub-50nm gate length nanotransistors, which incorporates the effects of the parasitics. The model accurately accounts for measurements of the S and Y parameters in the frequency range from 1 to 50GHz.

An ultra high-density hybrid integration for micro-electromechanical system (MEMS) mirror chips with several thousand inputs/outputs has been developed. The integration scheme involving flip-chip assembly provides electrical signal to individual mirrors, which is compatible with postprocessing steps of selectively removing the silicon handle and releasing the MEMS mirrors. For the first time, to our knowledge, solder deposition and flip-chip bonding of 3-mum bumps on 5-mum centers of a large array has been demonstrated.

The coupling of light to surface plasmons through periodic subwavelength metallic structures could strongly modify the optical properties of a metal film. We demonstrate that the optical transmission through an array of subwavelength slits is as high as 80% at resonance, even though the width of each slit is almost 10 times smaller than the wavelength and the slits occupy only 25% of the area of the metal. Numerical calculations suggest that the field intensity is strongly enhanced near the metal surface. The field enhancement could be used for generating nonlinear optical effects and for high sensitivity detection of nanomechanical displacement.

A new approach is presented for fabricating monolithic crystalline silicon tilting-mirror microoptoelectromechanical systems (MOEMS) devices. The activation electrodes, etched from a thick silicon layer deposited over insulating oxide onto the top surface of a silicon-on-insulator (SOI) wafer, are displaced from the mirrors and interact with these tilting elements via electrostatic fringing fields. In contrast to the more usual parallel-plate activation, the rotation angle saturates at high voltages. This paper discusses concept, design, and processing, and also compares modeling and measured performance of a specific 9/spl deg/ tilt range device array.

We have fabricated and demonstrated a new device called the vertical replacement-gate (VRG) MOSFET. This is the first MOSFET ever built in which: (1) all critical transistor dimensions are controlled preciselywithout lithographyand dryetch, (2) the gate length is defined bya deposited film thickness, independentlyof lithographyand etch, and (3) a high-qualitygate oxide is grown on a single-cry stal Si channel. In addition to this unique combination, the VRG-MOSFET includes self-aligned source/drain extensions (SDEs) formed bysolid source diffusion (SSD), small parasitic overlap, junction, and source/drain capacitances, and a replacement-gate approach to enable alternative gate stacks. We have demonstrated nMOSFETs with an initial VRG process, and pMOSFETs with a more mature process. Since both sides of the device pillar drive in parallel, the drive current per lm of coded width can far exceed that of advanced planar MOSFETs. Our 100 nm VRG-pMOSFETs with tOX ¼ 25 A drive 615 lA/lm at 1.5 V with IOFF ¼ 8 nA/lm—80% more drive than specified in the 1999 ITRS Roadmap at the same IOFF. Our 50 nm VRGpMOSFETs with tOX ¼ 25 A approach the 1.0 V roadmap target of ION ¼ 350 lA/l ma tIOFF ¼ 20 nA/lm without the need for a hyperthin (

The exponential growth of the silicon industry can be attributed to that fact that silicon has a native oxide that is silicon dioxide. With SiO 2 soon approaching its fundamental limit, we must find an alternate to SiO 2 or a new switch to replace MOSFETs. In this paper we focus on the leading alternate gate dielectrics. We first discuss the selection criteria for alternate gate dielectrics and why it is important to have an amorphous gate dielectric. SiO 2 and aluminum oxide remain amorphous at very high temperatures. For dielectrics with K >15 and gate power 2 , it may be necessary to stabilize the amorphous phase of metal oxides by adding Al or Si to the oxide, thus forming multi-component dielectrics such as aluminates. We then benchmark aluminates with aluminum oxide and silicon dioxide.

Alternating phase shift technology has been shown to substantially improve focus latitude and resolution for several years. However, the use of phase shift masks to improve the process latitude in gate level lithography has been hindered by the lack of commercially available tools that can convert conventional gate layouts into phase shift mask patterns. A software package has recently become available that allows a user to create phase shift masks to reduce the gate length of features in existing circuit layouts. A digital signal processing chip with 2 million gates has been used as a test vehicle to evaluate the feasibility of phase shifting and processing a large number of devices in a complete circuit. Three wafer lots have been processed with a target feature size of 120 nm with a variation of 25 nm 3σ. The timing circuits of the chips have been tested; those with 120 nm gates showed a nearly fourfold improvement in speed when compared to 240 nm gate circuits at 1 volt operation.

We discuss the fabrication of a FLASH EEPROM floating gate memory device with a cell size of 0.0896@mm. The floating gate level utilized an alternating aperture phase shift mask, a binary mask was used to expose the control gate level. Linewidth changes over topography, due to reflectivity variations, was controlled by an inorganic multilayer anti-reflective coating^1. All levels were exposed with a new generation of photoresists developed at Bell Laboratories with ARCH chemicals. Experiments were carried out to give some insight to the behavior of the materials and the viability of optical enhancement techniques. We have found that 193nm lithography with this new family of photoresists is reasonably proficient in the fabrication of devices with design rules of less than half the exposure wavelength.

To demonstrate the effectiveness of alternating aperture phase shift lithography and 193nm wavelength lithography for integrated circuit technology, two demonstration devices were designed and processed. In one case, a 2 million transistor integrated circuit was processed with phase shifting and 248nm wavelength lithography. Gate lengths were reduced from 240 to 120nm, resulting in a 100MHz circuit speed at 1.0 volt operation, a threefold improvement. In the second case an 80nm floating gate memory device was fabricated with phase shifting, 193nm wavelength lithography, and anti-reflection control. The lithographic results were confirmed by careful measurements throughout the process sequences and finally by the performance of the devices themselves.

SCALPEL alignment marks have been fabricated in a SiO 2 /WSi 2 structure using SCALPEL lithography and plasma processing. The positions of the marks were detected through e-beam resist in the SCALPEL proof of lithography (SPOL) tool by scanning the image of the corresponding mask mark over the wafer mark and detecting the backscattered electron signal. Single scans of line space patterns yielded mark positions that were repeatable within 30 nm 3σ with a dose of 0.4 μC/cm 2 and signal-to-noise of 16 dB. An analysis shows that the measured repeatability is consistent with a random noise limited response. The mark detection repeatability limit, that can be attributed to SPOL machine factors, was measured to be 20 nm 3σ. By using a digitally sequenced mark pattern, the capture range of the mark detection was increased to 13 μm while maintaining 36 nm 3σ precision. The SPOL machine mark detection results are very promising considering that they were measured under electron optical conditions that were not optimized.

A nanopore is an analytical tool with single molecule sensitivity. For detection, a nanopore relies on the electrical signal that develops when a molecule translocates through it. However, the detection sensitivity can be adversely affected by noise and the frequency response. Here, we report measurements of the frequency and noise performance of nanopores

A copper/air-gap interconnection structure using a sacrificial polymer and SiO/sub 2/ in a damascene process has been demonstrated. The air-gap occupies the entire intralevel volume with fully densified SiO/sub 2/ as the planar interlevel dielectric. The copper was deposited by physical vapor deposition and planarized by chemical-mechanical planarization. The Ta/Cu barrier/seed layer was deposited by physical vapor deposition; the bulk copper was electrochemically deposited. The resulting structure has an effective intralevel dielectric constant of 2.19.

Thin SiO2 layers were exposed to an HBr/O2 plasma for a variety of short periods, reproducing the over-etching process after polycrystalline Si gate electrodes have been etched and the gate oxide layer is exposed. Samples were transferred under vacuum to an x-ray photoelectron spectrometer for analysis. After relatively thick (>60 A) films were exposed to a 10% O2/HBr plasma at an average ion energy of ∼150 eV, the near-surface region becomes brominated, and the thickness of the film decreases, indicating an etching rate of ∼1–2 A/s. When the starting film thickness is between 10 and 20 A, however, exposure to the plasma results in an increases in the thickness of the film, and is enhanced with the increasing addition of oxygen to the feed gas. At mean ion energies of 40 or 150 eV, the transition from etching to deposition occurs at oxygen additions of ∼1% or ∼8%, respectively. The increase in SiO2 thickness is ascribed mainly to oxidation of the Si at the oxide-substrate interface, and not to deposition ...

Kinoform lenses avoid the absorption losses from a comparable refractive lens by removing all material causing redundant 2π phase shifts. Such optics allow high resolution imaging with a theoretical 94% focusing efficiency. While fabrication of kinoform lenses for two-dimensional focusing is difficult, standard lithographic processes can be utilized to fabricate optics in silicon which produce a line focus. By putting two single-dimension kinoform lenses in a crossed-pair arrangement, a two-dimensional spot is achieved. First attempts at imaging with a crossed pair of kinoform lenses are presented.

This paper discusses a significant improvement of the SOI process that can be implemented in various manners and that remedies many problems of earlier fabrication schemes. In particular the new MOEMS structures are monolithic, do not exhibit rotational snapdown, have electrical shielding between channels, and have activation voltages less than or comparable to parallel plate devices. The approach is discussed in terms of an application requiring a linear array of closely-spaced cantilever mirrors.

We demonstrate for the first time that chemical oxide underlayers /spl sim/5 /spl Aring/ thick provide improved growth and flatband voltage control of ALD HfO/sub 2/ films compared to thermal oxides. Optimized annealing conditions are shown to greatly reduce both fixed charge and interfacial oxide growth in the high-/spl kappa/ stacks. Extremely small flatband voltage shifts of

We report the fabrication and device characteristics of a 50 /spl Aring/ thick dual-layer gate dielectric with high interface quality (D/sub it/ and Q/sub f/ /spl sim/10/sup 10/ cm/sup 2/) and capable of retarding boron penetration. This dual-layer dielectric is formed by low temperature CVD deposition of a /spl sim/40 /spl Aring/ thick oxynitride layer, through which slow O/sub 2/ diffusion is used to grow a /spl sim/10 /spl Aring/ thick SiO/sub 2/ at the interface. The small thickness of the SiO/sub 2/ layer reduces the oxidation time at high temperature, thus reducing the required thermal budget. The top oxynitride retards boron penetration and the thin SiO/sub 2/ layer provides a high quality interface. The channel mobility of NMOS devices with this dual dielectric is equal to the mobility of devices with a RTO dielectric grown at 950/spl deg/C. >

Reports measurements of the DC characteristics of sub-100nm pMOSFETs that employ low leakage, ultra-thin gate oxides only 1-2nm thick and ultra-shallow junctions to achieve high current drive capability and transconductance. We demonstrate that I/sub Dsct/=0.23mA//spl mu/m can be achieved with a L/sub x/=65nm physical gate length at 15V using a 1.5nm gate oxide with a gate leakage current less than 20nA//spl mu/m/sup 2/ on devices without silicided contacts. But more importantly, we find no evidence of boron penetration through SiO/sub 2/ gate oxides as thin as 1.3nm, grown at 1000C using rapid thermal oxidation (RTO). Furthermore, for the first time, we have directly imaged the ultra-shallow p-n junctions that comprise a sub-100nm pMOSFET with an effective channel length of 20nm to show that the lateral extent of the junction is approximately half that of the vertical junction depth. We surmise that the enhanced vertical diffusion has an adverse effect on subthreshold characteristic of sub-100nm pMOSFETs.

Reports measurements of the DC characteristics of sub-100 nm nMOSFETs that employ low leakage ultra-thin gate oxides only 1-2 nm thick to achieve high current drive capability and transconductance. We demonstrate that I/sub Dsat//spl ap/1.8 mA//spl mu/m can be achieved with a 60 nm gate at 1.5 V using a 1.3-1.4 nm gate oxide with a gate leakage current less than 20 nA//spl mu/m/sup 2/. Furthermore, we find that I/sub Dsat/ deteriorates for gate oxides thicker or thinner than this.

A 1296-port MEMS transparent optical crossconnect with 5.1dB/spl plusmn/1.1dB insertion loss at 1550 nm is reported. Measured worst-case optical crosstalk in a fabric was n38 dB and nominal switching rise/fall times were 5 ms. A 2.07 petabit/s switch capacity was verified upon cross-connecting a forty-channel by 40 Gb/s DWDM data stream through a prototype fabric.

We present the first p-channel Vertical Replacement-Gate (VRG) MOSFETs. Like the VRG-nMOSFETs demonstrated last year, these devices show promise as a successor to planar MOSFETs for highly-scaled ULSI. Our pMOSFETs retain the key features of the nMOSFETs and add channel doping by ion implantation and raised source/drain extensions (SDEs). We have significantly improved the core VRG process to provide high-performance devices with gate lengths of 100 nm and below. Since both sides of the device pillar drive in parallel, the drive current per /spl mu/m of coded width can far exceed that of planar MOSFETs. Our 100 nm VRG-pMOSFETs with t/sub ox/=25 /spl Aring/ drive 615 /spl mu/A//spl mu/m at 1.5 V with I/sub OFF/=8 nA//spl mu/m-80% more drive than specified in the 1999 ITRS Roadmap at the same I/sub OFF/. We demonstrate 50 nm VRG-pMOSFETs with t/sub ox/=25 /spl Aring/ that approach the 1.0 V roadmap target of I/sub ON/=350 /spl mu/A//spl mu/m at I/sub OFF/=20 nA//spl mu/m without the need for a hyperthin (

This paper describes the fabrication, and structural and electrical characterization of a new, aerosol-nanocrystal floating-gate FET, aimed at non-volatile memory (NVM) applications. This aerosol- nanocrystal NVM device features program/erase characteristics comparable to conventional stacked gate NVM devices, excellent endurance (>105 P/E cycles), and long-term non-volatility in spite of a thin bottom oxide (55-60Å). In addition, a very simple fabrication process makes this aerosol-nanocrystal NVM device a potential candidate for low cost NVM applications.

The properties of sub-resolution assist features for 193nm wavelength contact window lithography have been investigated. A test mask consisting of a variety of window and assist feature sizes and pattern density environments was fabricated and printed. Windows, 160nm in diameter, where exposed in conventional and quadrupole off-axis illumination. Results show a substantial increase in depth- of-focus when quadruple illumination and assist features were employed, when compared to conventional illumination and standard contacts. The improved process latitude is especially apparent in thicker resist formulations, which are required for etching. By employing improved resists with assist features and quadrupole illumination, isolated 160 nm contacts have been fabricated in 510 nm thick resist on 1000 nm SiO2, without anti-reflective coatings. The depth-of- focus is approximately 0.5 microns. BY lowering the numerical aperture of the projection optics, the measured depth-of-focus is unchanged, but assist feature printing can be significantly reduced. Preliminary results of 160 nm windows etched into oxide show that resist loss may be unacceptable with conventional pattern transfer processes.

A manufacturable process for fabricating alignment marks that are compatible the SCALPEL lithography system is described. The marks were fabricated in a SiO 2 /WSi 2 structure using SCALPEL lithography and plasma processing. The positions of the marks were detected through e-beam resist in the SCALPEL proof of lithography (SPOL) tool by scanning the image of the corresponding mask mark over the wafer mark and detecting the backscattered electron (BSE) signal. Scans of 1 μm line-space patterns yielded mark positions that were repeatable within 20 nm 3σ with a dose of 4 μC/cm 2 and signal-to-noise of 32 dB. An analysis shows that the measured repeatability is consistent with a random noise limited response combined with SPOL machine factors. By using a digitally sequenced mark pattern, the capture range of the mark detection was increased to 13 μm while maintaining 36 nm 3σ precision. Further improvements in mark detection repeatability are expected when the SCALPEL electron optics is fully optimized.

This article reviews technology issues in scaling conventional planar transistors to a physical gate length of 30nm that are expected to produce an effective channel length of 10 nm. Gate fabrication features direct write e-beam lithography to form a ring structure capable of exploring the practical limits of gate processing while requiring only a single level of lithography. Other processing elements include ultra-thin gate dielectric formation (∼ 0.6nm); highly selective transformer coupled plasma (TCP) etching; and low energy ion implantation. DC electrical results obtained for high performance n-MOS and p-MOS type nanotransistors made using this process are discussed as are simulations of sub-threshold currents for n-MOS transistors with physical gate lengths down to 26nm

We demonstrate a half wave plate whose principle of operation is based on the strong evanescent field coupling between two metal layers with arrays of subwavelength slits. The device is divided into two kinds of pixels in which the slits are oriented in orthogonal directions. By tuning the phase delay of the transmitted light through the lateral displacement between the top and bottom layers, the polarization of linearly polarized light at 1.55 μm can be rotated by up to 90°. The polarization extinction ratio of the transmitted light exceeds 22 dB.

We demonstrate that the phase of light transmitted through double-layer subwavelength metallic slit arrays can be controlled through lateral shift of the two layers. Our samples consist of two aluminum layers, each of which contains an array of subwavelength slits. The two layers are placed in sufficient proximity to allow coupling of the evanescent fields at resonance. By changing the lateral shift between the layers from zero to half the period, the phase of the transmitted electromagnetic field is increased by pi, while the transmitted intensity remains high. Such a controllable phase delay could open new capabilities for nanophotonic devices that cannot be achieved with single-layer structures.

We present measurements of transmission of infrared radiation through double-layer metallic grating structures. Each metal layer contains an array of subwavelength slits and supports transmission resonance in the absence of the other layer. The two metal layers are fabricated in close proximity to allow coupling of the evanescent field on individual layers. The transmission of the double layer is found to be surprisingly large at particular wavelengths, even when no direct line of sight exists through the structure as a result of the lateral shifts between the two layers. We perform numerical simulations using rigorous coupled wave analysis to explain the strong dependence of the peak transmission on the lateral shift between the metal layers.

Spatial light modulators (SLMs) designed to replace photomasks for optical lithography have been designed, fabricated, and tested. These microelectromechanical devices are fabricated with alternating polycrystalline Si and sacrificial SiO2 layers that are patterned by a 193nm wavelength scanner to dimensions as small as 150nm. Aerial image simulations were used to define the mechanical requirements of the devices. Piston motion of electrically actuated devices was measured with an optical profilometer. The measurements were fit to a simple equation to within 1nm precision, which is adequate for defining 50nm features lithographically. Transient response measurements show that one version of the SLM responds to actuation as quickly as 20μs, fast enough for current 193nm wavelength excimer laser sources.

Zone plates are the key focusing element for many x-ray (7–20 keV) and soft x-ray (200–500 eV) applications, yet, production with electron-beam lithography poses obstacles to their widespread availability. In addition, fabrication processes to date have limited the studies of amplitude Bragg–Fresnel-type elements in the hard x-ray regime. We report new processes that couple 100 keV electron-beam lithography with established production methods to achieve two goals: (1) improving the overall yield and volume of ultrahigh-resolution soft x-ray zone plates and (2) applying deep silicon etching techniques to extend the state of the art in high aspect ratio Bragg–Fresnel optics required to create high efficiency focusing of high-energy x rays.

The narrowest feature of an integrated circuit is the silicon dioxide gate dielectric (3–5 nm). The viability of future CMOS technology is contingent upon thinning the oxide further to improve drive performance, while maintaining reliability. Practical limitations due to direct tunneling through the gate oxide may preclude the use of silicon dioxide as the gate dielectric for thicknesses less than 1.3 nm, however.

We have demonstrated a channelized micro-mechanical filter with 5 dB insertion loss and high extinction suitable for use as a channelized equalizing filter. The pass bands have been demonstrated to be sufficiently wide to permit its use with 40 Gb/s CSRZ signals.