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The first SiC integrated circuit linear voltage regulator is reported. The voltage regulator uses a 20-V supply and generates an output of 15 V, adjustable down to 10 V. It was designed for loads of up to 2 A over a temperature range of 25-225 °C. It was, however, successfully tested up to 300 °C. The voltage regulator demonstrated load regulations of 1.49% and 9% for a 2-A load at temperatures of 25 and 300 °C, respectively. However, the load regulation is less than 2% up to 300 °C for a 1-A load. The line regulation with a 2-A load at 25 and 300 °C was 17 and 296 mV/V, respectively. The regulator was fabricated in a Cree 4H-SiC 2-μm experimental process and consists of 1000, 32/2-μm NMOS depletion MOSFETs as the pass device, an integrated error amplifier with enhancement MOSFETs, and resistor loads, and uses external feedback and compensation networks to ensure operational integrity. It was designed to be integrated with high-voltage vertical power MOSFETs on the same SiC substrate. It also serves as a guide to future attempts for voltage regulation in any type of integrated SiC circuitry.

This paper presents the SPICE model development of the static characteristics of silicon carbide (SiC) lateral n-channel and p-channel MOSFETs based on the widely used BSIM4 compact model. The methodology for length and width scaling of the MOSFETs is demonstrated. The transfer ( $I_{\text{D}}$ – $V_{\text{G}}$ ) and output ( $I_{\text{D}}$ – $V_{\text{D}}$ ) characteristics of the SiC low-voltage MOSFETs are significantly different from their Si counterparts mainly due to the presence of the interface trapped charge, and proper modifications of the dc equations are required to accurately model the characteristics. The relatively poorer quality of the oxide-semiconductor interface in a SiC MOSFET compared to Si gives rise to valid energy states inside the bandgap. The trapped charges in these interface states are responsible for mobility degradation, higher subthreshold slope (SS), soft saturation, increase in the flat band and threshold voltage, and exaggerated body effects. In this paper, the effects of the interface trapped charge on the static characteristics of the SiC MOSFETs are intensively studied and accurate compact models are developed and incorporated in the core BSIM4 dc current equations to accurately model the SiC MOSFET ${I}$ – ${V}$ behavior. A new parameter extraction sequence is also proposed to optimize the model and the simulated characteristics are matched with the measured characteristics of SiC MOSFET devices.

This paper presents an 8-b digital to analog converter (DAC) and 8-b analog to digital converter (ADC) for high-temperature applications. The pair of data converters were designed in a 1.2- $\mu \text{m}$ silicon carbide CMOS process and have been tested from 25 °C to 400 °C. At 400 °C, the DAC has a maximum differential nonlinearity (DNL) and integral nonlinearity (INL) error of 1.2 least significant bit (LSB) and 2.7 LSB, respectively, while the offset and the gain error are 5.9 and 2.7 LSB. The ADC has a maximum DNL and INL error of 3.6 and −3 LSB, respectively, while the offset error is −7 LSB and the gain error is 2.6 LSB. The ADC has an SNDR = 32.15 dB and effective number of bits = 5.05 b at 300 °C. The DAC is the first of its kind in silicon carbide CMOS, while the ADC is the first reported at temperatures over 300 °C.

The work described herein applies a patented integrated silicon carbide (SiC) bipolar junction transistor (BJT) to the detection of ultraviolet (UV) light in situ for extreme-temperature environments. An integrated SiC BJT provides four important capabilities for UV detection in extreme environments: (1) The miniaturization of detectors and readout circuits through micron-scaled integrated circuit (IC) lithography; (2) the high-temperature operation of SiC ICs; (3) long-term reliability of SiC at high temperatures; and (4) the deep-UV responsivity of 4H-SiC. The design, manufacture and electrical characterization of a SiC photo-transistor is described. Photonic characterization of the photo-transistor responsivity in the vacuum ultraviolet (VUV) and near UV is analyzed. It will be shown that integration of the photo-transistor with SiC CMOS [1] advances the state-of-the-art to a photo-BiCMOS capability. The advancement of the state of the art is validated in both terrestrial and space-born applications, specifically (1) the patent-pending detection of the ultraviolet signature produced by the charge-compression auto-ignition of diesel fuel in a working 4-stroke engine, and (2) the measurement of Solar UV intensity in Low-Earth Orbit (LEO).

In the last decade, significant effort has been expended towards the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field effect transistors and metal-oxide-semiconductor field effect transistors have been pursued and demonstrated. More recently1,2, advances in low-power complementary MOS devices have enabled the development of highly-integrated digital, analog and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) for extended periods (up to 100 hours) of several building block circuits will be presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at these extreme temperatures for any period of time. Based on these results, Venus nominal temperature (470°C) SPICE m°dels and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

The design and test of the first undervoltage lock-out circuit implemented in a low-voltage 4H silicon carbide process capable of single-chip integration with power MOSFETs is presented. The lock-out circuit, a block of the protection circuitry of a single-chip gate driver topology designed for use in a plug-in hybrid vehicle charger, was demonstrated to have rise/fall times compatible with a MOSFET switching speed of 250 kHz while operating over the targeted operating temperature range between 0°C and 200°C. Captured data show the circuit to be functional over a temperature range from -55°C to 300°C. The design of the circuit and test results is presented.

A gate buffer fabricated in a 2-μm 4H silicon carbide (SiC) process is presented. The circuit is composed of an input buffer stage with a push-pull output stage, and is fabricated using enhancement mode N-channel FETs in a process optimized for SiC power switching devices. Simulation and measurement results of the fabricated gate buffer are presented and compared for operation at various voltage supply levels, with a capacitive load of 2 nF. Details of the design including layout specifics, simulation results, and directions for future improvement of this buffer are presented. In addition, plans for its incorporation into an isolated high-side/low-side gate-driver architecture, fully integrated with power switching devices in a SiC process, are briefly discussed. This letter represents the first reported MOSFET-based gate buffer fabricated in 4H SiC.

Silicon Carbide (SiC) integrated circuits processes show promise for improved performance in high temperature, high radiation, and other extreme environments. The circuits described are the first implementations of phase-locked or delay-locked loops in SiC. The PLL utilizes a common charge-pump topology including a fully integrated passive loop filter, and were designed with a target maximum operating frequency of 5 MHz. Component blocks use novel topologies to optimize performance in a SiC CMOS process. Experimental results of both the complete PLL as well as the Phase Frequency Detector and Voltage Controlled Oscillator components are presented. Operation of the PLL at frequencies up to 1.5 MHz is demonstrated through test results of unpackaged die.

In this work, the first reported integrated silicon carbide (SiC) CMOS gate driver is presented. The gate driver is designed in a 15V, 1.2 µm silicon carbide CMOS process, and simulated from 25 °C to 300 µC. The gate drivers are packaged and tested over a wide temperature range. Measured peak output current exceeds the 4 A source, 8 A sink current design goals at room temperature. The measured gate driver rise and fall times are 74.2 ns and 36.8 ns, respectively, while driving a SiC power MOSFET at a package temperature above 500 µC. Switching operation is demonstrated while at temperature.

A series of “standard” parts for use in extreme environments based on high-temperature silicon carbide complimentary logic is presented. High temperature results and statistical samples are used to demonstrate the maturity of the parts for extreme environment applications.

This paper describes the simulation and test results of a family of analog and mixed signal circuits in silicon carbide CMOS technology at temperatures of 300°C and above. As SiC and wide bandgap devices in general grow in popularity for efficient and stable operation in high temperature and harsh environment applications, CMOS SiC integrated circuits can open up a new frontier of opportunity for miniaturization and system dependability. The building block circuits presented here can serve as the basis of rugged SiC system-on-chips for extreme environment applications.

A family of X-band MMIC power amplifiers using a low cost GaAs pHEMT process is reported. The stepper-based volume 0.5 micron and 0.25 micron GaAs pHEMT processes utilize 4 inter-level metallisation and four dielectric layers for high frequency performance whilst maintaining the economies of scale of 150mm (6") diameter substrates. The fabricated GaAs X-Band PA MMICs exhibit SW to low NY output power under pulsed conditions; 16dB of power gain and power added efficiencies approaching 40%. Excellent repeatability and high yields over a number of wafers have been demonstrated. The design and GaAs process approach taken here with DUV stepper and 150 mm wafer diameter will lead to a significant cost reduction for high performance power amplifier MMICs up to 30GHz.

Supertwisted nematic (STN) liquid crystal displays remain a leading technology for mobile communications applications, personal digital assistants (PDA) and personal convergence devices. Higher demands on display information content place ever increasing demands on the physical parameters of the liquid crystal mixture. To satisfy current and future display requirements, it is necessary to develop mixtures showing: ? Fast response times achieved by rotational viscosity reduction and birefringence increase. ? Small temperature dependence of the operating voltage (dV/dT), especially at low temperatures. ? Small frequency dependence of the operating voltage (dV/df), necessary for multi-level greyscale operation. ? Improved steepness (V90/V10) of the electro-optical curve to enable higher duty multiplexing of the display. In order to fulfil these requirements, liquid crystal mixtures with improved physical properties were developed. Examples of these mixtures are presented.

This paper presents the testing results of an all-silicon carbide (SiC) intelligent power module (IPM) for use in future high-density power electronics applications. The IPM has high-temperature capability and contains both SiC power devices and SiC gate driver integrated circuits (ICs). The high-temperature capability of the SiC gate driver ICs allows for them to be packaged into the power module and be located physically close to the power devices. This provides a distinct advantage by reducing the gate driver loop inductance, which promotes high frequency operation, while also reducing the overall volume of the system through higher levels of integration. The power module was tested in a bridgeless-boost converter to showcase the performance of the module in a system level application. The converter was initially operated with a switching frequency of 200 kHz with a peak output power of approximately 5 kW. The efficiency of the converter was then evaluated experimentally and optimized by increasing the overdrive voltage on the SiC gate driver ICs. Overall a peak efficiency of 97.7% was measured at 3.0 kW output. The converter s switching frequency was then increased to 500 kHz to prove the high frequency capability of the power module was then pushedmore » to its limits and operated at a switching frequency of 500 kHz. With no further optimization of components, the converter was able to operate under these conditions and showed a peak efficiency of 95.0% at an output power of 2.1 kW.« less

Limitations of silicon (Si) based power electronic devices can be overcome with Silicon Carbide (SiC) because of its remarkable material properties. SiC is a wide bandgap semiconductor material with larger bandgap, lower leakage currents, higher breakdown electric field, and higher thermal conductivity, which promotes higher switching frequencies for high power applications, higher temperature operation, and results in higher power density devices relative to Si [1]. The proposed work is focused on design of a SiC gate driver to drive a SiC power MOSFET, on a Cree SiC process, with rise/fall times (less than 100 ns) suitable for 500 kHz to 1 MHz switching frequency applications. A process optimized gate driver topology design which is significantly different from generic Si circuit design is proposed. The ultimate goal of the project is to integrate this gate driver into a Toyota Prius plug-in hybrid electric vehicle (PHEV) charger module. The application of this high frequency charger will result in lighter, smaller, cheaper, and a more efficient power electronics system.

Filtronic Compound Semiconductors has developed the first 0.15μm process on 150mm GaAs pHEMT using deep UV stepper based technology for millimeter wave applications. The use of stepper technology allows for improved throughput and yield compared to E-beam lithography. The process has an FT of 85GHz with breakdown voltage of 15V and is ideally suited for power applications up to 40GHz. The pHEMTs have demonstrated output power of more than 1W/mm that to our knowledge is the highest reported power from a 0.15μm GaAs pHEMT process.

The central goal of these studies has been the integration of organic and inorganic components into well-defined structures using chemically functionalized viral capsids. Key strategies that have been explored include the use of new bioconjugation reactions to modify previously inaccessible sites on the protein surfaces and the preparation of water-soluble gold particles bearing reactive groups for biomolecules attachment. We have also developed a method for the attachment to viral capsids to carbon nanotubes using a new class of polymer-based surfactants.

A family of X-Band MMIC power amplifiers using a low cost GaAs pHEMT process is reported. The stepper based volume 0.5 micron and 0.25 micron GaAs pHEMT processes utilize 4 inter-level metallisation and four dielectric layers for high frequency performance whilst maintaining the economies of scale of 150 mm (6") diameter substrates. The fabricated GaAs X-Band PA MMICs exhibit 5 W to 10 W RF output power under pulsed conditions; 16 dB of power gain and power added efficiencies approaching 40%. Excellent repeatability and high yields over a number of wafers have been demonstrated. The design and GaAs process approach taken here with DUV stepper and 150 mm wafer diameter will lead to a significant cost reduction for high performance power amplifier MMICs up to 30 GHz.

Key parameters for any bistable device are operating voltage and temperature range. The development of liquid crystal mixtures for use with grating aligned Zenithal Bistable Displays (ZBD™) is described for the first time. Latching at voltages less than 5V, with 20V addressing faster than 80μs per line and operation over a temperature range from −20°C to 80°C are all demonstrated in the same 4μm device.